Continuous time linear equalization

Patent metadata

Field	Value
Publication number	US-10263815-B1
Application number	US-201715837928-A
Country	US
Kind code	B1
Filing date	Dec 11, 2017
Priority date	Dec 11, 2017
Publication date	Apr 16, 2019
Grant date	Apr 16, 2019

Abstract

This disclosure relates generally to continuous time linear equalization. In an example of a continuous time linear equalizer, a variable gain circuit includes transistors having gate nodes respectively as a first and a second input node. A first transimpedance circuit is connected between the first input node and a first output node. A second transimpedance circuit is connected between the second input node and a second output node. A source node of each of the first transistor and the second transistor are commonly connected to one another. In the same or another equalizer, output nodes of a first frequency peaking circuit are connected to input nodes of a second frequency peaking circuit. In such a same or another equalizer, an RC feedback circuit has tap-off nodes and summing nodes respectively connected at the output nodes of the first frequency peaking circuit.

First claim

What is claimed is:

1. A continuous time linear equalizer, comprising:
a variable gain circuit, the variable gain circuit comprising:
a first transistor and a second transistor each having a gate node respectively configured as a first input node and a second input node of the variable gain circuit, the first transistor and the second transistor each having a drain node respectively configured as a first output node and a second output node of the variable gain circuit;
a first transimpedance circuit connected between the first input node and the second output node of the variable gain circuit;
a second transimpedance circuit connected between the second input node and the first output node of the variable gain circuit; and
a source node of each of the first transistor and the second transistor commonly connected to one another.

2. The continuous time linear equalizer according to claim 1 , further comprising:
a first load circuit and a second load circuit commonly connected to a supply node and respectively connected to the first transimpedance circuit and the second transimpedance circuit;
a current source circuit connected between the source node and a ground node; and
wherein the first transimpedance circuit and the second transimpedance circuit are respectively configured to provide a first transimpedance and a second transimpedance to provide a transimpedance amplifier-like function for a variable gain function of the variable gain circuit.

3. The continuous time linear equalizer according to claim 1 , further comprising a voltage-to-current converter circuit having output nodes respectively connected to the first input node and the second input node of the variable gain circuit.

4. The continuous time linear equalizer according to claim 3 , wherein the variable gain circuit and the voltage-to-current converter circuit are respectively configured as a first current-mode logic buffer and a second current-mode logic buffer with the first transimpedance circuit and the second transimpedance circuit connected to provide feedback from the first current-mode logic buffer back to the second current-mode logic buffer.

5. The continuous time linear equalizer according to claim 4 , further comprising:
a resistor-capacitor (“RC”) feedback circuit configured with combined tap-off and summing nodes respectively in common with input nodes of the voltage-to-current converter circuit; and
wherein the first transimpedance circuit and the second transimpedance circuit respectively include a first resistance circuit and a second resistance circuit respectively configured to provide a first adjustable impedance and a second adjustable impedance.

6. A continuous time linear equalizer, comprising:
a first frequency peaking circuit and a second frequency peaking circuit;
output nodes of the first frequency peaking circuit connected to input nodes of the second frequency peaking circuit; and
the second frequency peaking circuit including:
a voltage-to-current converter circuit having the input nodes; and
a resistor-capacitor (“RC”) feedback circuit configured with combined tap-off and summing nodes respectively in common with the output nodes of the first frequency peaking circuit and the input nodes of the voltage-to-current converter circuit.

7. The continuous time linear equalizer according to claim 6 , wherein the voltage-to-current converter circuit is a first voltage-to-current converter circuit having a differential pair of transistors with commonly connected source nodes and respective gate nodes as the input nodes of the first voltage-to-current converter circuit, and wherein the RC feedback circuit comprises:
a buffer circuit having gate nodes respectively connected to the output nodes of the first frequency peaking circuit;
a filter circuit connected to drain nodes of the buffer circuit; and
a second voltage-to-current converter circuit connected to filter nodes of the filter circuit, the second voltage-to-current converter circuit having drain nodes respectively connected to the output nodes of the first frequency peaking circuit.

8. The continuous time linear equalizer according to claim 7 , wherein:
the buffer circuit is configured as a first current-mode logic buffer circuit; and
the second voltage-to-current converter circuit is configured as a second current-mode logic buffer circuit.

9. The continuous time linear equalizer according to claim 6 , wherein the second frequency peaking circuit comprises a variable gain control circuit connected to output nodes of the voltage-to-current converter circuit.

10. The continuous time linear equalizer according to claim 9 , wherein the variable gain control circuit comprises:
a first transimpedance circuit and a second transimpedance circuit respectively connected between the output nodes of the voltage-to-current converter circuit and output nodes of the variable gain control circuit to provide feedback for the second frequency peaking circuit; and
source nodes of the variable gain control circuit commonly connected to one another.

11. The continuous time linear equalizer according to claim 6 , further comprising:
a digital-to-analog converter connected to provide a first control signal and a second control signal respectively to an adjustable current source of each of the first frequency peaking circuit and the RC feedback circuit; and
wherein the second control signal is an inverse of the first control signal.

12. The continuous time linear equalizer according to claim 11 , wherein the voltage-to-current converter circuit is a first voltage-to-current converter circuit having a differential pair of transistors with commonly connected source nodes and respective gate nodes as the input nodes of the first voltage-to-current converter circuit, and wherein the RC feedback circuit comprises:
a buffer circuit having gate nodes respectively connected to the output nodes of the first frequency peaking circuit;
a filter circuit connected to drain nodes of the buffer circuit;
a second voltage-to-current converter circuit connected to filter nodes of the filter circuit, the second voltage-to-current converter circuit having drain nodes respectively connected to the output nodes of the first frequency peaking circuit; and
the second voltage-to-current converter circuit including the adjustable current source of the RC feedback circuit.

13. The continuous time linear equalizer according to claim 11 , wherein the voltage-to-current converter circuit is a first voltage-to-current converter circuit having a differential pair of transistors with commonly connected source nodes and respective gate nodes as the input nodes of the first voltage-to-current converter circuit, and wherein the RC feedback circuit comprises:
a buffer circuit having gate nodes respectively connected to the output nodes of the first frequency peaking circuit;
a filter circuit connected to drain nodes of the buffer circuit;
a second voltage-to-current converter circuit connected to filter nodes of the filter circuit, the second voltage-to-current converter circuit having drain nodes respectively connected to the output nodes of the first frequency peaking circuit; and
the buffer circuit including the adjustable current source of the RC feedback circuit.

14. The continuous time linear equalizer according to claim 11 , wherein:
the first frequency peaking circuit is for first frequencies; and
the second frequency peaking circuit is for second frequencies either less than the first frequencies or greater than or equal to the first frequencies.

15. A method for continuous ti

Assignees

• Xilinx Inc

Inventors

• Geary Kevin
• Carey Declan
• Elzeftawi Mohamed

Classifications

• H03K19/1774

  for global signals, e.g. clock, reset · CPC title

• H03G2201/103

  being an amplifying element · CPC title

• H03G3/3089

  Control of digital or coded signals · CPC title

• H04L25/03878 Primary

  Line equalisers; line build-out devices · CPC title

• H03G3/001

  Digital control of analog signals · CPC title