Semiconductor chip

Patent metadata

Field	Value
Publication number	US-10263143-B2
Application number	US-201815948650-A
Country	US
Kind code	B2
Filing date	Apr 9, 2018
Priority date	Apr 12, 2017
Publication date	Apr 16, 2019
Grant date	Apr 16, 2019

Abstract

A semiconductor chip ( 20 ) is described comprising a semiconductor layer sequence ( 10 ) based on a phosphide compound semiconductor material or arsenide compound semiconductor material wherein the semiconductor layer sequence ( 10 ) contains a p-type semiconductor region ( 4 ) and an n-type semiconductor region ( 2 ). The n-type semiconductor region ( 2 ) comprises a superlattice structure ( 20 ) for improving current spreading, wherein the superlattice structure ( 20 ) has a periodic array of semiconductor layers ( 21, 22, 23, 24 ). A period of the superlattice structure ( 20 ) has at least one undoped first semiconductor layer ( 21 ) and a doped second semiconductor layer ( 22 ), wherein an electronic band gap E 2 of the doped second semiconductor layer ( 22 ) is larger than an electronic band gap E 1 of the undoped first semiconductor layer ( 21 ).

First claim

The invention claimed is:

1. A semiconductor chip having a semiconductor layer sequence having one or more layers comprising a III-phosphide compound semiconductor material or III-arsenide compound semiconductor material, wherein the semiconductor layer sequence contains a p-type semiconductor region and an n-type semiconductor region, wherein
the n-type semiconductor region comprises a superlattice structure for improving current spreading, the superlattice structure having a periodic arrangement of semiconductor layers,
a period of the superlattice structure has at least one undoped first semiconductor layer and a doped second semiconductor layer, an electronic band gap E 2 of the doped second semiconductor layer being larger than an electronic band gap E 1 of the undoped first semiconductor layer,
the undoped first semiconductor layer is arranged in the superlattice structure in each case between an undoped first intermediate layer and an undoped second intermediate layer.

2. The semiconductor chip according to claim 1 ,
wherein the undoped first semiconductor layer comprises In 0.5 Al x1 Ga 0.5-x1 P, where 0≤x1≤0.27, or Al y1 Ga 1-y1 As, where 0≤y1<0.4, and the doped second semiconductor layer comprises In 0.5 Al x2 Ga 0.5-x2 P, where 0≤x2≤0.5 and x1<x2, or Al y2 Ga 1-y2 As, where 0<y2≤1 and y1<y2.

3. The semiconductor chip according to claim 2 ,
wherein the aluminum content x1 of the undoped first semiconductor layer is less than 0.25.

4. The semiconductor chip according to claim 1 ,
wherein the doped second semiconductor layer has a dopant concentration between 1×10 16 cm −3 and 1×10 20 cm −3 .

5. The semiconductor chip according to claim 1 ,
wherein a thickness of the undoped first semiconductor layer is between 3 nm and 15 nm.

6. The semiconductor chip according to claim 1 ,
wherein a thickness of the doped second semiconductor layer is between 20 nm and 30 nm.

7. The semiconductor chip according to claim 1 ,
wherein the undoped first intermediate layer and the undoped second intermediate layer have the same electronic band gap E 2 as the doped second semiconductor layer.

8. The semiconductor chip according to claim 1 ,
wherein a thickness of the undoped first intermediate layer and/or the undoped second intermediate layer is between 0.5 nm and 20 nm.

9. The semiconductor chip according to claim 1 ,
wherein the superlattice structure has between 5 and 70 periods.

10. The semiconductor chip according to claim 1 ,
wherein a specific resistance of the superlattice structure is less than 0.05 Ωcm.

11. The semiconductor chip according to claim 1 ,
wherein the semiconductor chip is an optoelectronic semiconductor chip, and the optoelectronic semiconductor chip has an active layer disposed between the p-type semiconductor region and the n-type semiconductor region.

12. The semiconductor chip according to claim 11 ,
wherein the active layer has a quantum well structure having at least one quantum well layer and at least one barrier layer, and wherein the electronic band gap E 1 of the undoped first semiconductor layer of the superlattice structure is larger than an electronic band gap E QW of the at least one quantum well layer of the quantum well structure.

13. A semiconductor chip having a semiconductor layer sequence having one or more layers comprising a III-phosphide compound semiconductor material or III-arsenide compound semiconductor material, wherein the semiconductor layer sequence contains a p-type semiconductor region and an n-type semiconductor region, wherein
the n-type semiconductor region comprises a superlattice structure for improving current spreading, the superlattice structure having a periodic arrangement of semiconductor layers,
a period of the superlattice structure has at least one undoped first semiconductor layer and a doped second semiconductor layer, an electronic band gap E 2 of the doped second semiconductor layer being larger than an electronic band gap E 1 of the undoped first semiconductor layer,
the undoped first semiconductor layer is arranged in the superlattice structure in each case between an undoped first intermediate layer and an undoped second intermediate layer,
the period of the superlattice structure consists of four layers, wherein in each period an undoped first intermediate layer, the undoped first semiconductor layer, an undoped second intermediate layer and the doped second semiconductor layer follow one another.

Assignees

• Osram Opto Semiconductors Gmbh

Inventors

• Wang Xue
• Broell Markus
• Barthel Stefan

Classifications

• H01L33/06 Primary

  Electricity · mapped topic

• H01L31/035263

  Electricity · mapped topic

• H01L31/03046

  Electricity · mapped topic

• H01L33/30

  Electricity · mapped topic

• H10H20/824

  comprising only Group III-V materials, e.g. GaP · CPC title