Semiconductor memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10263008-B2
Application number	US-201614986853-A
Country	US
Kind code	B2
Filing date	Jan 4, 2016
Priority date	Jul 14, 2015
Publication date	Apr 16, 2019
Grant date	Apr 16, 2019

Abstract

According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a first insulating layer. The plurality of control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The first insulating layer is positioned between the semiconductor layer and the control gate electrode. In addition, part of the first insulating layer is a charge accumulation layer. Moreover, part of the first insulating layer is an oxide layer positioned upwardly of the charge accumulation layer.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a plurality of control gate electrodes stacked above a substrate;
a semiconductor layer having as its longitudinal direction a direction perpendicular to the substrate, the semiconductor layer facing the plurality of control gate electrodes;
a first insulating layer positioned between the semiconductor layer and one of the plurality of the control gate electrodes, a first part of the first insulating layer being a charge accumulation layer, and a second part of the first insulating layer being an oxide layer positioned upwardly of the charge accumulation layer; and
a second insulating layer positioned between the semiconductor layer and the first insulating layer, the second insulating layer contacting the charge accumulation layer and the oxide layer,
a boundary of the charge accumulation layer and the oxide layer including an inclined portion extending through the charge accumulation layer and the oxide layer and extending from a position closer to the control gate electrodes to a position closer to the semiconductor layer, the oxide layer not extending beyond a lower portion of the inclined portion of the boundary, and
at least one of the plurality of the control gate electrodes facing the semiconductor layer through the inclined portion of the boundary of the charge accumulation layer and the oxide layer.

2. The semiconductor memory device according to claim 1 , further comprising:
a third insulating layer provided between the first insulating layer and the control gate electrode.

3. The semiconductor memory device according to claim 1 , wherein
the plurality of control gate electrodes include a first control gate electrode and a second control gate electrode positioned more upwardly than the first control gate electrode, and
the boundary of the charge accumulation layer and the oxide layer is positioned more upwardly than the first control gate electrode and more downwardly than an upper surface of the second control gate electrode.

4. The semiconductor memory device according to claim 3 , comprising:
a memory string including a plurality of memory cells connected in series; and
a select gate transistor connected to one end of the memory string,
wherein the first control gate electrode functions as a control gate electrode of the memory cell, and
the second control gate electrode functions as a control gate electrode of the select gate transistor.

5. The semiconductor memory device according to claim 4 , wherein
the plurality of control gate electrodes include a plurality of the second control gate electrodes, and
the boundary of the charge accumulation layer and the oxide layer is positioned more downwardly than a lower surface of the second control gate electrode positioned in a lowermost layer.

6. The semiconductor memory device according to claim 4 , further comprising
a dummy memory cell provided between the memory cell and the select gate transistor,
wherein the plurality of control gate electrodes further include a third control gate electrode positioned between the first control gate electrode and the second control gate electrode, and
the third control gate electrode functions as a control gate electrode of the dummy memory cell.

7. The semiconductor memory device according to claim 3 , further comprising:
a third insulating layer between the second control gate electrode and the first insulating layer, wherein
the third insulating layer contacts the charge accumulation layer and the second control gate electrode.

8. The semiconductor memory device according to claim 3 , further comprising:
an inter-layer insulating layer provided between the first control gate electrode and the second control gate electrode; and
a fourth insulating layer provided between the inter-layer insulating layer and the charge accumulation layer.

9. The semiconductor memory device according to claim 1 , wherein
a boundary line of the boundary of the charge accumulation layer and the oxide layer is a curved line.

10. The semiconductor memory device according to claim 1 , wherein the second insulating layer physically contacts the charge accumulation layer and the oxide layer.

Assignees

• Toshiba Memory Corp

Inventors

• Nishida Daisuke
• Sekine Katsuyuki
• Ishigaki Hirokazu
• Shimura Yasuhiro

Classifications

• H10P14/6532

  by exposure to a plasma · CPC title

• H10P14/6522

  introduced into a nitride material, e.g. changing SiN to SiON · CPC title

• H10P14/6319

  Formation by plasma treatments, e.g. plasma oxidation of the substrate · CPC title

• H10P14/6304

  Formation by oxidation, e.g. oxidation of the substrate · CPC title

• H01L21/02252

  Electricity · mapped topic