Drive system and drive method of liquid crystal display

Patent metadata

Field	Value
Publication number	US-10262579-B2
Application number	US-201615300977-A
Country	US
Kind code	B2
Filing date	Jul 14, 2016
Priority date	May 25, 2016
Publication date	Apr 16, 2019
Grant date	Apr 16, 2019

Abstract

There provides a drive system for a liquid crystal display, which includes: a timing controller for generating a scanning start signal; a level shifter for boosting the generated scanning start signal and generating at least one clock signal according to the boosted scanning start signal; and a gate driver for scanning and driving gate lines according to the boosted scanning start signal and the generated clock signal. There also provides a drive method of a liquid crystal display. With the drive system and drive method of a liquid crystal display provided in the present invention, it can reduce the pins required by the timing controller and the level shifter, thus the packages of the timing controller and the level shifter get smaller, thereby reducing the package cost.

First claim

The invention claimed is:

1. A drive system for a liquid crystal display, comprising:
a timing controller for generating a scanning start signal;
a level shifter for boosting the generated scanning start signal and generating at least one clock signal according to the boosted scanning start signal; and
a gate driver for scanning and driving gate lines according to the boosted scanning start signal and the clock signal; and
wherein the level shifter receives the scanning start signal generated by the timing controller as one single signal supplied from the timing controller to the level shifter and generates, from the scanning start signal, the boosted scanning signal and the at least one clock signal that is generated by delaying a rising edge of the boosted scanning start signal by a delay time so that the boosted scanning start signal and the at least one clock signal are determined by the scanning start signal that is supplied as one single signal from the timing controller to the level shifter and the delay time, wherein the at least one clock signal lags behind the boosted scanning signal by the delay time.

2. The drive system of claim 1 , wherein the level shifter is also used to store at least one preset value that determines the delay time, and to perform a delay operation on the boosted scanning start signal according to the stored preset value, so as to delay the rising edge of the boosted scanning start signal by the delay time to generate the at least one clock signal.

3. The drive system of claim 2 , wherein the level shifter is also used to perform the delay operation on the boosted scanning start signal according to the stored preset value so as to generate the clock signal, when the rising edge of the boosted scanning start signal is detected.

4. The drive system of claim 3 , wherein the level shifter comprises:
a boost module for boosting the generated scanning start signal;
a storage module for storing the at least one preset value;
a detection module for detecting the rising edge of the boosted scanning start signal;
a delay module for acquiring the at least one preset value from the storage module when the detection module detects the rising edge of the boosted scanning start signal, and performing the delay operation on the boosted scanning start signal according to the acquired preset value, so as to generate the at least one clock signal; and
an output module for outputting the boosted scanning start signal and the clock signal.

5. The drive system of claim 4 , wherein the at least one preset value stored in the storage module comprises at least two preset values including a minimum preset value and a maximum preset value, and the delay module acquire the at least two preset values successively in an order from the minimum preset value to the maximum preset value, and perform the delay operation on the boosted scanning start signal according to each of the at least two preset values so acquired, so as to generate a clock signal corresponding to each of the at least two preset values.

6. The drive system of claim 5 , wherein the delay time by which the rising edge of the boosted scanning start signal is delayed is such that the delay time gets longer successively in an order from the minimum preset value to the maximum preset value.

7. The drive system of claim 1 , wherein the timing controller and the level shifter are assembled on a Printed Circuit Board Assembly (PCBA), and
the level shifter comprises: an IIC protocol module for communicating with a connector on the PCBA.

8. A drive method of a liquid crystal display, comprising:
generating a single scanning start signal;
boosting the single scanning start signal to generate a boosted scanning start signal;
generating a clock signal according to the boosted scanning start signal; and
scanning and driving gate lines according to the boosted scanning start signal and the clock signal;
wherein the clock signal is generated by delaying a rising edge of the boosted scanning start signal by a delay time so that the boosted scanning start signal and the clock signal are determined by the single scanning start signal and the delay time such that the at least one clock signal lags behind the boosted scanning signal by the delay time.

9. The drive method of claim 8 , wherein the clock signal that is generated according to the boosted scanning start signal is generated with a process that comprises the following steps:
detecting the rising edge of the boosted scanning start signal;
acquiring a stored preset value when the rising edge of the boosted scanning start signal is detected;
performing a delay operation on the boosted scanning start signal according to the acquired preset value, so as to delay the rising edge of the boosted scanning start signal by the delay time to generate the clock signal; and
outputting the boosted scanning start signal and the clock signal.

10. The drive method of claim 9 , wherein when at least two preset values including a minimum preset value and a maximum preset value are stored, the at least two preset values are acquired successively in an order from the minimum preset value to the maximum preset value, and the delay operation is performed on the boosted scanning start signal according to each of the at least two preset values so acquired, so as to generate a clock signal corresponding to each of the at least two preset values, and
wherein the delay time by which the rising edge of the boosted scanning start signal is delayed is such that the delay time gets longer successively in an order from the minimum preset value to the maximum preset value.

Assignees

• Shenzhen China Star Optoelect

Inventors

• Zeng Dekang

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2370/08

  Details of image data interface between the display device controller and the data line driver circuit · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G3/3688

  suitable for active matrices only · CPC title

• G09G3/2096 Primary

  Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167) · CPC title