System on a chip and method for a controller supported virtual machine monitor

Patent metadata

Field	Value
Publication number	US-10261817-B2
Application number	US-201414445788-A
Country	US
Kind code	B2
Filing date	Jul 29, 2014
Priority date	Jul 29, 2014
Publication date	Apr 16, 2019
Grant date	Apr 16, 2019

Abstract

A system on a chip comprising: a first communication controller; at least one second communication controller operably coupled to the first communication controller; at least one processing core operably coupled to the first communication controller and arranged to support software running on a first partition and a second partition; and a virtual machine monitor located between the first and second partitions, and the at least one processing core and arranged to support communications there between. The first communication controller is arranged to: generate or receive at least one data frame; and communicate the at least one data frame to the at least one second communication controller; such that the at least one second communication controller is capable of routing the at least one data frame to the second partition bypassing the virtual machine monitor.

First claim

The invention claimed is:

1. A system on a chip comprising:
a first communication controller circuit;
a second communication controller circuit operably coupled to the first communication controller circuit;
a crossbar interface circuit to provide communication between the first communication controller circuit and the second communication controller circuit;
a processing core operably coupled to the first communication controller and arranged to support software running on a first partition and a second partition; and
a virtual machine monitor circuit located between the first and second partitions, and the processing core and arranged to support communications between the first and second partitions, the virtual machine monitor circuit to route a first data frame from the first partition to the second partition;
the first communication controller circuit is arranged to:
receive a second data frame from a component external to the system on a chip; and
communicate the second data frame to the second communication controller circuit via the crossbar interface circuit;

in response to the second data frame being received at the second communication controller circuit, the second communication controller circuit to route the second data frame to the second partition bypassing the virtual machine monitor circuit, wherein bypassing the virtual machine monitor circuit by the second communication controller circuit comprises:
offloading functionality from the virtual machine monitor circuit by bypassing, in part or completely, virtual machine monitor circuit functionality selected from a group comprising fan-out, interrupt handling, parts of error handling, and read and write access on datagram buffers, while retaining control by the virtual machine monitor circuit of common communication controller properties selected from a group comprising clock gates and a bitrate; and
extending functionality of the second communication controller circuit to allow functionality enhancement and concurrent accesses; wherein enhancing functionality comprises enhancing one or more of a first host controller interface, a protocol engine circuit, or one or more data buffers.

2. The system on a chip of claim 1 wherein the first communication controller circuit is arranged to create a copy of the data frame and route the copy to the second communication controller circuit.

3. The system on a chip of claim 2 wherein the second communication controller circuit routes the copy of the data frame to the second partition and the first communication controller circuit routes the data frame to the first partition.

4. The system on a chip of claim 1 wherein the processing core comprises a first processing core operably coupled to the first communication controller circuit and arranged to support software running on a first partition and a second processing core arranged to support software running on a second partition.

5. The system on a chip of claim 1 wherein partitions are mapped to one or multiple cores.

6. The system on a chip of claim 1 wherein the processing core hosts one or more partitions.

7. The system on a chip of claim 1 wherein the first communication controller circuit comprises plurality of components comprising at least one from a group consisting of: the first host controller interface circuit, the protocol engine circuit operably coupled to the first host controller interface circuit, the one or more data buffers, and a bus interface circuit.

8. The system on a chip of claim 7 wherein at least one of the plurality of components is arranged to perform its function for both the first communication controller circuit and the second communication controller circuit.

9. The system on a chip of claim 7 wherein the second communication controller circuit comprises a subset of the first communication controller circuit's plurality of components.

10. The system on a chip of claim 9 wherein each second communication controller circuit comprises only a second host controller interface circuit.

11. The system on a chip of claim 10 wherein a number of second communication controller circuits are operably coupled to the same number of second partitions in bypassing the virtual machine monitor circuit.

12. The system on a chip of claim 9 wherein the first communication controller circuit and the second communication controller circuit are operably coupled to each other via the first host controller interface circuit and a second host controller interface circuit.

13. The system on a chip of claim 12 wherein the first host controller interface circuit and the second host controller interface circuit are arranged to support serialization and synchronization of concurrent accesses to and from the first communication controller circuit.

14. The system on a chip of claim 9 wherein the second communication controller circuit comprises at least one from a group of: a second host controller interface circuit, the protocol engine circuit operably coupled to the second host controller interface circuit, and a data buffer.

15. The system on a chip of claim 14 wherein the protocol engine circuit of the second communication controller circuit is arranged to receive a completely decoded datagram from a first protocol engine circuit of the first communication controller circuit and serve its own copy of the data buffer and second host controller interface circuit.

16. The system on a chip of claim 14 further comprising a communication bus located between a first protocol engine circuit and the first host controller interface circuit of the first communication controller circuit and the second host controller interface circuit of the second communication controller circuit wherein the communication bus is arranged to arbitrate host controller interface circuit accesses and replicate control flow from the first protocol engine circuit to the first host controller interface circuit.

17. The system on a chip of claim 1 wherein the data frame bypassing the virtual machine monitor circuit comprises at least one from a group of: fan-out, received first-in first-out information, interrupt handling, error handling, and read and write access on datagram buffers.

18. The system on a chip of claim 1 wherein second communication controller circuit is arranged to capture and interrogate the data that it receives and transfers from/to the first communication controller circuit.

19. The system on a chip of claim 1 wherein the first partition and the second partition operate asynchronously.

20. A method for a controller supported virtual machine monitor located between first and second partitions of a processing core in a system on a chip, wherein the system on a chip comprises: a crossbar interface; a first communication controller; a second communication controller operably coupled to the first communication controller via the crossbar interface; wherein the method comprises:
running software, by the processing core operably coupled to the first communication controller, on the first partition and the second partition;
supporting, by the virtual machine monitor, communications between the first and second partitions and the processing core;
routing, by the virtual machine monitor, a first data frame from the first partition to the second partition, wherein the first data frame is generated internally at the first partition;
receiving a second data frame by the first communication controller from a component external to the system on a chip;
communicating

Assignees

• Steinert Frank
• Baumeister Markus
• Nxp Usa Inc

Inventors

• Steinert Frank
• Baumeister Markus

Classifications

• G06F2009/45595

  Network integration; Enabling network access in virtual machine instances · CPC title

• G06F9/45558 Primary

  Hypervisor-specific management and integration aspects · CPC title

• G06F2009/45579

  I/O management, e.g. providing access to device drivers or storage · CPC title