Board edge connector

Patent metadata

Field	Value
Publication number	US-10257944-B2
Application number	US-201615378570-A
Country	US
Kind code	B2
Filing date	Dec 14, 2016
Priority date	Dec 14, 2016
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

Apparatuses and methods for forming serial advanced technology attachment (SATA) board edge connectors with electroplated hard gold contacts. One example method can include forming a tie bar on an inner layer of a printed circuit board (PCB), forming a trace on an outer layer of the PCB, forming a via, wherein the via electrically couples the tie bar to the trace, forming a contact coupled to the trace on the outer layer, and sending an electrical charge from the tie bar through the via and the trace to the contact to electroplate the contact.

First claim

What is claimed is:

1. A method comprising:
forming a tie bar on an inner layer of a printed circuit board (PCB);
forming a trace on an outer layer of the PCB
forming a via, wherein the via electrically couples the tie bar to the trace;
forming a contact coupled to the trace on the outer layer; and
sending an electrical charge from the tie bar through the via and the trace to the contact to electroplate the contact.

2. The method of claim 1 , wherein the contact is being electroplated with gold.

3. The method of claim 1 , wherein the via is removed after the contact is electroplated.

4. The method of claim 3 , wherein the via is removed by drilling the via.

5. The method of claim 4 , wherein the drilling the via electrically disconnects the tie bar from the contact.

6. A method comprising:
forming a tie bar on an inner layer of a printed circuit board (PCB);
forming a trace on an outer layer of the PCB;
forming a via, wherein the via electrically couples the tie bar to the trace;
forming a contact coupled to the trace on the outer layer;
sending an electrical charge from the tie bar through the via and the trace to the contact to electroplate the contact; and
removing the via.

7. The method of claim 6 , wherein the contact does not have parasitic loading.

8. The method of claim 6 , wherein the trace manufacturing includes etching.

Assignees

• Micron Technology Inc

Inventors

• Smith Kurt B

Classifications

• H05K1/111

  Pads for surface mounting, e.g. lay-out · CPC title

• H05K1/117

  Pads along the edge of rigid circuit boards, e.g. for pluggable connectors · CPC title

• H05K1/114

  Pad being close to via, but not surrounding the via · CPC title

• H05K3/423 Primary

  characterised by electroplating method · CPC title

• H01R12/721 Primary

  cooperating directly with the edge of the rigid printed circuits · CPC title