Display substrate and manufacturing method thereof, display device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10256425-B2
Application number	US-201615544727-A
Country	US
Kind code	B2
Filing date	Mar 9, 2016
Priority date	Apr 24, 2015
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

The present disclosure provides a display substrate, comprising: a bending resistant region; the region comprises a base and a metal wire layer, wherein the metal wire layer is directly formed on the base, or the region further comprises an organic buffer layer located between the base and the metal wire layer, and the metal wire layer is directly formed on the organic buffer layer. The present disclosure provides a method for manufacturing the display substrate above-described. The present disclosure further provides a display device, comprising the display substrate above-described. The present disclosure further provides a method for manufacturing the display device, comprising the method for manufacturing the display substrate above-described. The present disclosure forms a bending resistant structure in a predetermined bending resistant region on the bezel portions of the display substrate, which can enhance the bend resistance thereof and improve the quality of the flexible display.

First claim

What is claimed is:

1. A display substrate, comprising:
a base;
a metal wire layer positioned on the base;
a first region;
a second region adjacent the first region, the base including a first base portion in the first region and a second base portion in the second region, and the metal wire layer including a first metal wire layer portion in the first region and a second metal wire layer portion in the second region; and
an inorganic layer insulating layer positioned on the second base portion, the second metal wire portion positioned on the inorganic insulating layer;
wherein the first metal wire layer portion is positioned directly on the first base portion, or an organic buffer layer is positioned between the first base portion and the first metal wire layer portion and the first metal wire layer portion is positioned directly on the organic buffer layer; and
wherein:
the inorganic insulating layer includes the inorganic buffer layer and a gate insulating layer and the metal wire layer includes a gate metal layer, and an interlayer insulating layer, a passivation layer, a planarization layer, a pixel defining layer and a packaging layer are sequentially positioned on the gate metal layer; or
the inorganic insulating layer includes the inorganic buffer layer, the gate insulating layer and an interlayer insulating layer, the metal wire layer includes a source and/or drain metal layer, and the passivation layer, the planarization layer, the pixel defining layer, and the packaging layer are sequentially positioned on the source and/or drain metal layer; or
the first metal wire layer portion is positioned directly on the first base portion and a thickness of the first metal wire layer portion is greater than or equal to a thickness of the second metal wire layer portion so an upper surface of the metal wire layer is flat.

2. The display substrate according to claim 1 , further comprising a display region and bezel regions on opposite sides of the display region, wherein the first region is located in the bezel regions.

3. The display substrate according to claim 1 , wherein the first metal wire layer portion is positioned directly on the first base portion and the thickness of the first metal wire layer portion is greater than or equal to the thickness of the second metal wire layer portion where the upper surface of the metal wire layer is flat.

4. The display substrate according to claim 1 , wherein the base comprises at least one of polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate and polyethylene naphthalate.

5. The display substrate according to claim 1 , wherein the packaging layer includes a plurality of alternate inorganic layers and organic layers.

6. The display substrate according to claim 1 , wherein the inorganic insulating layer comprises the inorganic buffer layer and the gate insulating layer, the metal wire layer includes the gate metal layer, and the interlayer insulating layer, the passivation layer, the planarization layer, the pixel defining layer and the packaging layer are sequentially formed on the gate metal layer.

7. The display substrate according to claim 6 , wherein the interlayer insulating layer and the passivation layer are discontinuous with the interlayer insulating layer and the passivation layer not positioned on the first metal wire layer portion.

8. The display substrate according to claim 1 , wherein the inorganic insulating layer comprises the inorganic buffer layer, the gate insulating layer and the interlayer insulating layer, the metal wire layer is the source and/or drain metal layer, and the passivation layer, the planarization layer, the pixel defining layer, and the packaging layer are sequentially positioned on the source and/or drain metal layer.

9. The display substrate according to claim 8 , wherein the passivation layer is discontinuous with the passivation layer not positioned on the first metal wire layer portion.

10. A display device comprising a display body including the display substrate according to claim 1 .

11. A method for manufacturing a display substrate, the method comprising:
providing a base including a first base portion and a second base portion adjacent the first base portion;
forming a metal wire layer on the base, with a first metal wire layer portion of the metal wire layer formed directly on a first base portion of the base, or an organic buffer layer provided between a first metal wire layer portion of the metal wire layer and the first base portion of the base and the first metal wire layer portion positioned directly on the organic buffer layer; and
at least one of:
forming the inorganic insulating layer on the first base portion and the second base portion, and removing the inorganic insulating layer on the first base portion; or
forming the inorganic insulating layer only on the second base portion so the inorganic insulating layer is positioned between the second base portion of the base and a second metal wire layer portion of the metal wire layer, the inorganic insulating layer including an inorganic buffer layer and a gate insulating layer, the metal wire layer including a gate metal layer, and sequentially forming an interlayer insulating layer, a passivation layer, a planarization layer, a pixel defining layer and a packaging layer on the gate metal layer; or
forming the inorganic insulating layer only on the second base portion so the inorganic insulating layer is positioned between the second base portion of the base and a second metal wire layer portion of the metal wire layer, the inorganic insulating layer including the inorganic buffer layer, the gate insulating layer and an interlayer insulating layer, the metal wire layer including a source and/or drain metal layer, and sequentially forming the passivation layer, the planarization layer, the pixel defining layer and the packaging layer on the source and/or drain metal layer.

12. The method according to claim 11 , wherein forming the inorganic insulating layer includes forming the inorganic insulating layer on the first base portion and the second base portion and removing the inorganic insulating layer on the first base portion.

13. The method according to claim 11 , wherein forming the packaging layer comprises:
alternately depositing a plurality of inorganic layers and organic layers to form the packaging layer.

14. The method according to claim 11 , wherein forming the inorganic insulating layer includes forming the inorganic insulating layer only on the second base portion with the inorganic insulating layer provided between the second base portion of the base and the second metal wire layer portion of the metal wire layer.

15. The method according to claim 14 , wherein the inorganic insulating layer comprises the inorganic buffer layer and the gate insulating layer, the metal wire layer includes the gate metal layer, and sequentially forming the layers includes sequentially forming the interlayer insulating layer, the passivation layer, the planarization layer, the pixel defining layer and the packaging layer on the gate metal layer.

16. The method according to claim 15 , wherein the interlayer insulating layer and the passivation layer are discontinuous with the interlayer insulating layer and the passivation layer not positioned on the first metal wire layer portion.

17. The method according to claim 14 , wherein the inorganic insulating layer comprises the inorganic buffer layer, the gate insulating layer and the interlayer insulating layer, the metal wire layer includes

Assignees

• Boe Technology Group Co Ltd

Inventors

• Cai Peng

Classifications

• H01L2227/323

  Electricity · mapped topic

• H01L51/5237

  Electricity · mapped topic

• H01L27/3246

  Electricity · mapped topic

• H01L2251/5338

  Electricity · mapped topic

• H01L51/56

  Electricity · mapped topic