Method of manufacturing solar cell

US10256364B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10256364-B2
Application numberUS-201715858016-A
CountryUS
Kind codeB2
Filing dateDec 29, 2017
Priority dateJun 10, 2015
Publication dateApr 9, 2019
Grant dateApr 9, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of manufacturing a solar cell, the method includes forming a protective film over a semiconductor substrate, the semiconductor substrate including a base area of a first conductive type and formed of crystalline silicon, wherein the forming of the protective film includes a heat treatment process performed at a heat treatment temperature of approximately 600 degrees Celsius or more under a gas atmosphere including nitrogen, and wherein the heat treatment process includes: a main section, during which the heat treatment temperature is maintained, a temperature increase section before the main section, during which an increase in temperature occurs from an introduction temperature to the heat treatment temperature, and a temperature reduction section after the main section, during which a decrease in temperature occurs from the heat treatment temperature to a discharge temperature.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of manufacturing a solar cell, the method comprising: forming a protective film over a semiconductor substrate, the semiconductor substrate including a base area of a first conductive type and formed of crystalline silicon, wherein the forming of the protective film includes a heat treatment process performed at a heat treatment temperature of approximately 600 degrees Celsius or more under a gas atmosphere including nitrogen, and wherein the heat treatment process includes: a main section, during which the heat treatment temperature is maintained, a temperature increase section before the main section, during which an increase in temperature occurs from an introduction temperature to the heat treatment temperature, and a temperature reduction section after the main section, during which a decrease in temperature occurs from the heat treatment temperature to a discharge temperature. 2. The method according to claim 1 , wherein the forming of the protective film includes at least one of the following: forming the protective film via thermal oxidation by performing the heat treatment process in a heat treatment furnace; forming the protective film via deposition by performing the heat treatment process in a low-pressure chemical vapor deposition device; and forming the protective film by performing a wet chemical process or a dry process of forming a preliminary protective film at a temperature of approximately 600 degrees Celsius or less, and thereafter thermally treating the preliminary protective film at a temperature of approximately 600 degrees Celsius or more via the heat treatment process. 3. The method according to claim 1 , wherein the gas atmosphere further includes oxygen gas as a source gas so that the protective film includes a silicon oxide layer. 4. The method according to claim 1 , wherein the heat treatment temperature of the heat treatment process is within a range from approximately 600 degrees Celsius to approximately 900 degrees Celsius. 5. The method according to claim 1 , wherein the introduction temperature or the discharge temperature is within a range from approximately 400 degrees Celsius to approximately 550 degrees Celsius. 6. The method according to claim 5 , wherein the introduction temperature or the discharge temperature is within a range from approximately 500 degrees Celsius to approximately 550 degrees Celsius. 7. The method according to claim 1 , further comprising, before the forming of the protective film, forming a conductive area, which is one of the first conductive type having a higher doping concentration than that of the base area and a second conductive type opposite to the first conductive type, by doping an inside of the semiconductor substrate with a dopant, wherein, in the forming the protective film, the protective film is then formed over the conductive area. 8. The method according to claim 7 , wherein the protective film has a thickness within a range from approximately 3 nm to 6 nm. 9. The method according to claim 1 , further comprising, before the forming of the protective film, forming a conductive area over one surface of the semiconductor substrate, the conductive area having a different crystalline structure from that of the semiconductor substrate, wherein, in the forming of the protective film, the protective film is then formed over the conductive area. 10. The method according to claim 9 , wherein, in the forming of the conductive area, a first conductive area, which is of the first conductive type, and a second conductive area, which is of the second conductive type opposite to the first conductive type, are formed in the same plane over one surface of the semiconductor substrate, and wherein the protective film covers both the first conductive area and the second conductive area. 11. The method according to claim 10 , wherein the protective film has a thickness within a range from approximately 3 nm to 6 nm. 12. The method according to claim 1 , wherein, in the forming of the protective film, the protective film is a control passivation layer formed over one surface of the semiconductor substrate, and wherein the method further comprises, after the forming of the protective film, forming a conductive area over the control passivation layer. 13. The method according to claim 12 , wherein, in the forming the conductive area, a first conductive area, which is of the first conductive type, and a second conductive area, which is of a second conductive type opposite to the first conductive type, are formed in the same plane over the control passivation layer. 14. The method according to claim 12 , wherein the control passivation layer has a thickness within a range from approximately 1 nm to 2 nm. 15. The method according to claim 1 , wherein the protective film is at least one of a first passivation film located over one surface of the semiconductor substrate and a second passivation film over a remaining surface of the semiconductor substrate. 16. The method according to claim 15 , wherein the first passivation film and the second passivation film are formed at the same time via the heat treatment process. 17. The method according to claim 1 , wherein the protective film is an anti-reflection film. 18. The method according to claim 1 , wherein the protective film includes at least one of silicon, carbon, oxygen and nitrogen. 19. The method according to claim 1 , wherein the introduction temperature and the discharge temperature are different from each other. 20. The method according to claim 1 , wherein processing times of the temperature increase section and the temperature reduction section are different from each other.

Assignees

Inventors

Classifications

  • the material being halogen doped silicon oxides, e.g. FSG · CPC title

  • by exposure to a gas or vapour · CPC title

  • Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

  • of silicon in uncombined form, i.e. pure silicon · CPC title

  • of treatments performed after formation of the materials · CPC title

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What does patent US10256364B2 cover?
A method of manufacturing a solar cell, the method includes forming a protective film over a semiconductor substrate, the semiconductor substrate including a base area of a first conductive type and formed of crystalline silicon, wherein the forming of the protective film includes a heat treatment process performed at a heat treatment temperature of approximately 600 degrees Celsius or more und…
Who is the assignee on this patent?
Lg Electronics Inc
What technology area does this patent fall under?
Primary CPC classification H01L31/1868. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 09 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).