Nonvolatile memory device

Patent metadata

Field	Value
Publication number	US-10256288-B2
Application number	US-201615769629-A
Country	US
Kind code	B2
Filing date	Aug 25, 2016
Priority date	Oct 20, 2015
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

A nonvolatile memory device can be manufactured without adding any major modification to a structure and component elements of a conventional MOS type silicon device, and is realized without deteriorating an electrical characteristic of an insulating-film/semiconductor interface and on the basis of a new operational principle. The nonvolatile memory device 10 is a capacitor configured by a metal electrode 16 , two kinds of insulating films 13 and 15 , and an interface structure of an insulating film 12 /semiconductor 11 , and has a MIS structure of providing a monolayer-level O-M 1 -O layer 14 to an insulating-film 13 /semiconductor 15 interface. The nonvolatile memory device 10 realizes a nonvolatile information storage operation by changing strength or polarities of interface dipoles induced near the O-M 1 -O layer 14 through electrical stimulation applied from a gate electrode.

First claim

What is claimed is:

1. A nonvolatile memory device comprising a capacitor structure stacked on a semiconductor or metal,
wherein the capacitor structure includes, on a bonding interface of two different insulating films, a monolayer-level O-M 1 -O layer in which oxygen (O) and a metallic element (M 1 ) other than component elements of the insulating films are chemically bonded, and
information is memorized by changing strength or polarities of interface dipoles induced near the monolayer-level O-M 1 -O layer through external electrical stimulation.

2. The nonvolatile memory device according to claim 1 ,
wherein each of the insulating films contains one oxide or more of oxide silicon, germanium oxide, hafnium oxide, zirconium oxide, lanthanum oxide, aluminum oxide, and yttrium oxide.

3. The nonvolatile memory device according to claim 1 ,
wherein the metallic element (M 1 ) is one element or more of magnesium, titanium, strontium, yttrium, lanthanum, tantalum, gallium, and antimony.

4. The nonvolatile memory device according to claim 1 ,
wherein the bonding interface having the O-M 1 -O layer includes two interfaces or more.

5. The nonvolatile memory device according to claim 1 ,
wherein the capacitor structure is formed on an insulating-film/semiconductor structure having low interface state density.

6. A three-terminal type nonvolatile memory device comprising:
second-conductive type first and second semiconductor regions formed on a first-conductive type semiconductor substrate, the second-conductive type first and second semiconductor regions being separated from and opposing each other; and
a gate structure body provided on a surface of the semiconductor substrate between the first and second semiconductor regions, the gate structure body comprising a capacitor structure and a metal electrode on the capacitor structure, the capacitor structure including a monolayer-level O-M 1 -O layer on a two different insulating films, oxygen (O) and a metallic element (M 1 ) other than component elements of the insulating films being chemically bonded in the monolayer-level O-M 1 -O layer; and
a field effect transistor structure having the metal electrode serving as a gate electrode, and the first and second semiconductor regions respectively serving as drain and source regions,
wherein information is memorized by changing strength or polarities of interface dipoles that the O-M 1 -O layer induces through an electrical signal applied to the gate electrode.

Assignees

• Aist

Inventors

• Miyata Noriyuki

Classifications

• H01L29/788

  Electricity · mapped topic

• H01L27/10

  Electricity · mapped topic

• H01L29/7882

  Electricity · mapped topic

• H01L29/792

  Electricity · mapped topic

• H01L29/517

  Electricity · mapped topic