System and method for display auto-correction impedance mismatch control

US10255876B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10255876-B2
Application numberUS-201615362593-A
CountryUS
Kind codeB2
Filing dateNov 28, 2016
Priority dateNov 28, 2016
Publication dateApr 9, 2019
Grant dateApr 9, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method and information handling system including a display device connector for connecting to a digital display device, a controller executing instructions of an impedance mismatch control system for determining impedance differences along an operative connection from the display device connector to the digital display device, where the controller receives a display device connector impedance measurement and a second impedance measurement from a point further along the operative connection between the display device connector and the digital display device, and the controller executes the impedance mismatch control system to determine an impedance mismatch exists from the impedance difference between the display device connector and the point further along the operative connection between the display device connector and the digital display device.

First claim

Opening claim text (preview).

What is claimed is: 1. An information handling system comprising: a display device connector for connecting to a digital display device; a controller executing instructions of an impedance mismatch control system for determining impedance differences along an operative connection from the display device connector to the digital display device; the controller receiving a display device connector first impedance measurement to detect impedance level of a motherboard and the display device connector of the information handling system and a second impedance measurement from a point further along the operative connection between the display device connector and the digital display device to detect impedance level of a currently-connected display control board and display cable or display trace; and the controller executing the impedance mismatch control system to determine an impedance mismatch level by determining that the impedance difference between the display device connector and the point further along the operative connection between the display device connector and the digital display device exceeds an impedance mismatch variance threshold level. 2. The information handling system of claim 1 further comprising: the controller transmitting a signal to adjust impedance via an impedance adjustment circuit. 3. The information handling system of claim 1 wherein the impedance mismatch variance threshold level is a difference of the display device connector impedance at +/−5% of the second impedence measurement. 4. The information handling system of claim 1 wherein the second impedance measurement from the point further along the operative connection between the display device connector and the digital display device is a digital display device connector cable impedance measurement. 5. The information handling system of claim 1 wherein the second impedance measurement from the point further along the operative connection between the display device connector and the digital display device is a digital display device control board impedance measurement. 6. The information handling system of claim 1 further comprising: an impedance adjustment circuit including a variable capacitor and at least one inductor in parallel; and the controller transmitting a signal to adjust the variable capacitor to adjust the first impedance of the digital display connector. 7. The information handling system of claim 1 further comprising: a directional coupler for measuring trace first impedance from the digital display connector. 8. A computerized method of impedance mismatch control for a display device connector in an information handling system comprising: executing instructions, via a controller, of an impedance mismatch control system for determining impedance differences along an operative connection from the display device connector to a digital display device; measuring a first impedance from a point further along the operative connection between the display device connector and the digital display device operatively connected to the information handling system to detect impedance level of a currently-connected display control board and display cable or display trace; measuring a second impedance of the display device connector device of the information handling system to detect impedance level of a motherboard and the display device connector; determining an impedance mismatch between the first impedance and the second impedance; and in response to determining the impedance mismatch, sending an adjustment signal to an impedance adjustment circuit to adjust the second impedance of the display device connector device. 9. The computerized method of claim 8 further comprising: sending the adjustment signal to adjust capacitance of a variable capacitor of the impedance adjustment circuit when the impedance mismatch is determined by the impedance mismatch control system. 10. The computerized method of claim 8 further comprising: sending the adjustment signal to decrease capacitance at a variable capacitor when the measured impedance of the display device connector is greater than an impedance mismatch variance threshold level above the second impedance measurement, wherein the variable capacitor is in parallel with an inductor of the impedance adjustment circuit. 11. The computerized method of claim 8 further comprising: sending the adjustment signal to increase capacitance at a variable capacitor when the measured second impedance of the display device connector is greater than a impedance mismatch variance threshold level below the first impedance measurement, wherein the variable capacitor is in parallel with an inductor of the impedance adjustment circuit. 12. The computerized method of claim 8 further comprising: sending the adjustment signal to increase capacitance at a variable capacitor when the measured second impedance of the display device connector is greater than an impedance mismatch variance threshold level above the first impedance measurement, wherein the variable capacitor is in series with an inductor of the impedance adjustment circuit. 13. The computerized method of claim 8 further comprising: sending the adjustment signal to decrease capacitance at a variable capacitor when the measured second impedance of the display device connector is greater than an impedance mismatch variance threshold level below the first impedance measurement, wherein the variable capacitor is in series with an inductor of the impedance adjustment circuit. 14. The computerized method of claim 8 further comprising: sending the adjustment signal to adjust inductance of a variable inductor when the impedance mismatch is determined by the impedance mismatch control system. 15. The computerized method of claim 8 wherein the first impedance is measured from a digital display device connector cable operatively connected to the display device connector. 16. An information handling system comprising: a display device connector for connecting to a digital display device; a controller executing instructions of an impedance mismatch control system for determining impedance differences along an operative connection from the display device connector to the digital display device; the controller receiving a first impedance measurement from a digital display device connector cable operatively connected to the display device connector to detect impedance level of the digital display device connector cable and a display device connector second impedance measurement of the display device connector to detect impedance level of a motherboard and the display device connector; and the controller executing the impedance mismatch control system to determine an impedance mismatch from a difference between the display device connector second impedance measurement and the first impedance measurement that exceeds an impedance mismatch variance threshold level. 17. The information handling system of claim 16 further comprising: an impedance adjustment circuit adjusting the impedance of the display device connector device in response to determining the impedance mismatch. 18. The information handling system of claim 16 wherein the impedance mismatch variance threshold level is +/−5% of the first impedance measurement. 19. The information handling system of claim 16 further comprising: the controller sending a signal to increase capacitance at a variable capacitor when the measured second impedance of the display device connector is greater than t

Assignees

Inventors

Classifications

  • Processor architectures; Processor configuration, e.g. pipelining · CPC title

  • G09G5/006Primary

    Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04) · CPC title

  • Details {; arrangements for supplying electrical power along data transmission lines (systems for transmitting signals via power distribution lines H04B3/54)} · CPC title

  • Test circuits or failure detection circuits included in a display system, as permanent part thereof · CPC title

  • Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared · CPC title

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What does patent US10255876B2 cover?
A method and information handling system including a display device connector for connecting to a digital display device, a controller executing instructions of an impedance mismatch control system for determining impedance differences along an operative connection from the display device connector to the digital display device, where the controller receives a display device connector impedance…
Who is the assignee on this patent?
Dell Products Lp
What technology area does this patent fall under?
Primary CPC classification G09G5/006. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Apr 09 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).