Task assembly for SIMD processing

Patent metadata

Field	Value
Publication number	US-10255653-B2
Application number	US-201715452569-A
Country	US
Kind code	B2
Filing date	Mar 7, 2017
Priority date	Mar 7, 2016
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

A cache system in a graphics processing system stores graphics data items for use in rendering primitives. It is determined whether graphics data items relating to primitives to be rendered are present in the cache, and if not then computation instances for generating the graphics data items are created. Computation instances are allocated to tasks using a task assembly unit which stores task entries for respective tasks. The task entries indicate which computation instances have been allocated to the respective tasks. The task entries are associated with characteristics of computation instances which can be allocated to the respective tasks. A computation instance to be executed is allocated to a task based on the characteristics of the computation instance. SIMD processing logic executes computation instances of a task outputted from the task assembly unit to thereby determine graphics data items, which can be used to render the primitives.

First claim

The invention claimed is:

1. A graphics processing system configured to render primitives, the graphics processing system comprising:
a cache system configured to:
store, in a cache, graphics data items for use in rendering primitives; and
determine whether graphics data items relating to primitives to be processed for rendering are present in the cache;

a task assembly unit configured to:
store a plurality of task entries for respective tasks to which computation instances can be allocated, the computation instances being for generating graphics data items which are determined by the cache system as being not present in the cache, wherein the task entries indicate which computation instances have been allocated to the respective tasks, and wherein the task entries are associated with characteristics of computation instances which can be allocated to the respective tasks;
allocate, to a task, a computation instance to be executed, based on the characteristics of the computation instance; and
output one or more tasks for execution;

SIMD processing logic configured to execute, in a SIMD manner, computation instances of a task outputted from the task assembly unit to thereby determine graphics data items for storage in the cache; and
primitive processing logic configured to render primitives using graphics data items stored in the cache.

2. The graphics processing system of claim 1 further comprising a task dependency unit configured to maintain indications of dependencies between different tasks for which task entries are stored in the task assembly unit.

3. The graphics processing system of claim 1 wherein the cache system is further configured to allocate portions of the cache to each of the computation instances allocated to tasks in the task assembly unit.

4. The graphics processing system of claim 3 wherein the task assembly unit is configured to flush one or more tasks for execution by the SIMD processing logic if the cache system cannot allocate a portion of the cache to one or more of the computation instances.

5. The graphics processing system of claim 1 wherein the cache system is further configured to lock portions of the cache which are allocated to computation instances relating to primitives to be processed for rendering.

6. The graphics processing system of claim 5 wherein the cache system is configured to store a state bit for each graphics data item in the cache to indicate whether the graphics data item is available or is scheduled for execution.

7. The graphics processing system of claim 1 wherein the characteristics of a computation instance include one or both of: (i) a shader type, and (ii) a state.

8. The graphics processing system of claim 1 wherein the graphics processing system is a tile-based graphics processing system configured to use a rendering space which is subdivided into a plurality of tiles, wherein the graphics processing system is configured to perform a rendering process for each of the tiles.

9. The graphics processing system of claim 8 wherein the task assembly unit is configured to be able to allocate computation instances relating to different tiles to a common task.

10. The graphics processing system of claim 8 wherein the graphics processing system is configured to process multiple tiles in parallel using respective tile processing pipelines.

11. The graphics processing system of claim 8 wherein the graphics processing system is configured to implement a geometry processing phase and a rasterisation phase,
wherein the geometry processing phase comprises: (i) receiving graphics data of input graphics data items, (ii) determining transformed positions within the rendering space of one or more primitives derived from the input graphics data items, and (iii) generating, for each of the tiles, control stream data including identifiers of input graphics data items which are to be used for rendering the tile, and primitive indications to indicate which of the primitives derived from the input graphics data items are to be used for rendering the tile; and
wherein the rasterisation phase comprises: (i) receiving the control stream data for a particular tile; and (ii) using the cache system to store graphics data items for use in rasterising primitives which the primitive indications of the received control stream data indicate are to be used for rendering the tile.

12. The graphics processing system of claim 11 wherein the cache system is configured to store a hierarchy of graphics data items in the cache, wherein graphics data items defining primitives to be rendered are derivable from one or more input graphics data items via a sequence of one or more processing stages, said hierarchy including one or both of: (i) one or more of the input graphics data items, and (ii) one or more graphics data items representing results of processing stages of the sequence.

13. The graphics processing system of claim 12 wherein the cache system is configured to retrieve graphics data items from the cache in a bottom-up manner.

14. The graphics processing system of claim 12 wherein the sequence of processing stages comprises implementing one or more of a vertex shader, a hull shader, a domain shader and a geometry shader.

15. The graphics processing system of claim 1 wherein the primitive processing logic comprises:
transform logic configured to perform transform operations on graphics data items retrieved from the cache relating to primitives to be processed for rendering;
a hidden surface removal unit configured to remove primitive fragments which are hidden; and
a texturing/shading unit configured to apply one or both of texturing and shading to primitive fragments.

16. The graphics processing system of claim 1 wherein the task assembly unit is configured to output a particular task for execution in response to:
the particular task being full;
a new task entry for a new task being ready to be written to the task assembly unit when the task assembly unit does not have available space for a new task entry;
a further task, which has one or more dependencies on the particular task, being

due to be executed; or
a flush of a rendering queue which includes a primitive to which the particular task relates.

17. The graphics processing system of claim 1 wherein the task assembly unit is configured to select a task to be output for execution.

18. The graphics processing system of claim 1 wherein the task assembly unit is configured to store:
(a) input and output references for computation instances of a task, wherein the input references for computation instances of a task are shared by the computation instances of the task;
(b) input and output references for computation instances of a task in one or more task slots, wherein the maximum number of references in a task slot is the same for the different task slots, and wherein the number of task slots per task varies for different tasks based on the number of inputs associated with computation instances included in the task;
(c) a task table and a primitive table, wherein the task table stores references to primitives used as inputs or outputs for computation instances in a task, and wherein the primitive table stores indications of vertices for primitives referenced in the task table; or
(d) output references for computation instances of a task, and wherein input references for computation instances are stored with shader data in the cache.

19. A method of processing primitives in a graphics processing system, the method comprisi

Assignees

• Imagination Tech Ltd

Inventors

• Sansottera Andrea
• Yang Xile
• Howson John
• Redshaw Jonathan

Classifications

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T15/80

  Shading · CPC title

• G06T1/60

  Memory management · CPC title

• G06T2210/52

  Parallel processing · CPC title

• G06T17/20

  Finite element generation, e.g. wire-frame surface description, {tesselation} · CPC title