System and method for performing shaped memory access operations

Patent metadata

Field	Value
Publication number	US-10255228-B2
Application number	US-201113312954-A
Country	US
Kind code	B2
Filing date	Dec 6, 2011
Priority date	Dec 6, 2011
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

One embodiment of the present invention sets forth a technique that provides an efficient way to retrieve operands from a register file. Specifically, the instruction dispatch unit receives one or more instructions, each of which includes one or more operands. Collectively, the operands are organized into one or more operand groups from which a shaped access may be formed. The operands are retrieved from the register file and stored in a collector. Once all operands are read and collected in the collector, the instruction dispatch unit transmits the instructions and corresponding operands to functional units within the streaming multiprocessor for execution. One advantage of the present invention is that multiple operands are retrieved from the register file in a single register access operation without resource conflict. Performance in retrieving operands from the register file is improved by forming shaped accesses that efficiently retrieve operands exhibiting recognized memory access patterns.

First claim

What is claimed is:

1. A computer-implemented method for performing register memory operations, the method comprising:
receiving an instruction that is to be executed across a plurality of operands;
organizing the plurality of operands into one or more operand groups based on a location of each operand within a bank of register files;
determining that a plurality of register files in which a first operand group is stored is accessible via a particular memory access pattern, wherein the plurality of register files is included in the bank of register files, and the first operand group is included in the one or more operand groups;
forming a shaped memory access operation corresponding to the particular memory access pattern; and
performing the shaped memory access operation to access the plurality of operands from the plurality of register files.

2. The method of claim 1 , wherein the shaped memory access operation is configured to access single-width operands.

3. A subsystem for performing register memory operations, comprising:
an instruction dispatch unit configured to:
receive an instruction that is to be executed across a plurality of operands;
organize the plurality of operands into one or more operand groups based on a location of each operand within a bank of register files;
determine that a plurality of register files in which a first operand group is stored is accessible via a particular memory access pattern, wherein the plurality of register files is included in the bank of register files, and the first operand group is included in the one or more operand groups;
form a shaped memory access operation corresponding to the particular memory access pattern; and
perform the shaped memory access operation to access the plurality of operands from the plurality of register files.

4. The subsystem of claim 3 , wherein the shaped memory access operation is configured to access single-width operands.

5. A computing device comprising:
a subsystem that includes an instruction dispatch unit configured to:
receive an instruction that is to be executed across a plurality of operands;
organize the plurality of operands into one or more operand groups based on a location of each operand within a bank of register files;
determine that a plurality of register files in which a first operand group is stored is accessible via a particular memory access pattern, wherein the plurality of register files is included in the bank of register files, and the first operand group is included in the one or more operand groups;
form a shaped memory access operation corresponding to the particular memory access pattern; and
perform the shaped memory access operation to access the plurality of operands from the plurality of register files.

6. The method of claim 1 , wherein the plurality of register files is organized into two or more logical banks based on the types of operands associated with the plurality of operands.

7. The method of claim 1 , wherein each register file included in the plurality of register files comprises a different plurality of registers, and each register included in the plurality of registers is identified with a thread identifier and a register identifier.

Assignees

• Qiu Xiaogang
• Choquette Jack Hilaire
• Gautho Manuel Olivier
• Siu Ming Y Michael
• Nvidia Corp

Inventors

• Qiu Xiaogang
• Choquette Jack Hilaire
• Gautho Manuel Olivier
• Siu Ming Y (Michael)

Classifications

• G06F9/383

  Operand prefetching (cache prefetching G06F12/0862) · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/3455

  using stride · CPC title

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F9/3012

  Organisation of register space, e.g. banked or distributed register file · CPC title