Method and apparatus for sub-page write protection

Patent metadata

Field	Value
Publication number	US-10255196-B2
Application number	US-201514979038-A
Country	US
Kind code	B2
Filing date	Dec 22, 2015
Priority date	Dec 22, 2015
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

An apparatus and method for sub-page extended page table protection. For example, one embodiment of an apparatus comprises: a page miss handler to perform a page walk using a guest physical address (GPA) and to detect whether a page identified with the GPA is mapped with sub-page permissions; a sub-page control storage to store at least one GPA and other data related to a sub-page; the page miss handler to determine whether the GPA is programmed in the sub-page control storage; and the page miss handler to send a translation to a translation lookaside buffer (TLB) with a sub-page protection indication set to cause a matching of the sub-page control storage when an access matches a TLB entry with sub-page protection indication.

First claim

What is claimed is:

1. A processor comprising:
a memory management unit implemented in a circuit, including a page miss handler to perform a page walk using a guest physical address (GPA) and to detect, by checking one or more sub-page permission bits within a memory page table, whether a page identified with the GPA is mapped with the one or more sub-page permission bits that indicate walking a sub-page protection table being enabled for the page, and wherein the sub-page protection table indicates read and write permissions of sub-pages;
a sub-page control storage to store at least one GPA and other sub-page-related data including an offset and operand size for the GPA; and
a write-allowed scratchpad register,
wherein the page miss handler is to determine whether the GPA is identified in the sub-page control storage, and
the page miss handler is to send a translation to a translation lookaside buffer (TLB) with a sub-page protection indication set to cause a matching of the sub-page related data when there is a TLB hit, the sub-page protection indication indicating the translation is for a sub-page TLB entry, wherein the TLB is further configured to match the offset and operand size for the GPA in the sub-page control storage, if a TLB entry with the sub-page protection indication was hit for an access, and wherein the TLB is to invoke one or more microcode assist operations to perform fault checking if there is no match of the offset and/or operand size when an access matches a TLB entry with sub-page protection indication, and
wherein when the one or more microcode assist operations are invoked by the page miss handler, the one or more microcode assist operations cache write-permission bits for the GPA into the write-allowed scratchpad register.

2. The processor as in claim 1 wherein if the GPA is not programmed in the sub-page control storage, then the page miss handler to invoke one or more microcode assist operations to perform fault checking.

3. The processor as in claim 1 wherein when the one or more microcode assist operations are invoked, the one or more microcode assist operations walk the sub-page protection table and program the sub-page control storage with an offset and operand size if the sub-page protection table indicates that the offset accessed by an assisting store is writeable.

4. The processor as in claim 3 wherein if the assisting store is not writeable, then an extended page table violation fault is triggered to notify a virtual machine monitor.

5. The processor as in claim 1 wherein the sub-page control storage comprises a valid indication to indicate whether the data contained therein is valid, a GPA indication, an address operand size indication, and an address offset indication.

6. The processor as in claim 2 further comprising:
a front-end unit comprising a non-inclusive instruction cache to store an instruction which triggered the one or more microcode assist operations, the one or more microcode assist operations to cause the instruction to be re-executed.

7. A method comprising:
performing a page walk using a guest physical address (GPA) and detecting, by checking one or more sub-page permission bits within a memory page table, whether a page identified with the GPA is mapped with the one or more sub-page permission bits that indicate walking a sub-page protection table being enabled for the page, and wherein the sub-page protection table indicates read and write permissions of sub-pages;
storing at least one GPA and other sub-page-related data including an offset and operand size for the GPA in a sub-page control storage;
determining whether the GPA is identified in the sub-page control storage;
sending a translation to a translation lookaside buffer (TLB) with a sub-page protection indication set to cause a match against data programmed in the sub-page control storage when there is a TLB hit, the sub-page protection indication indicating the translation is for a sub-page TLB entry;
matching the offset and operand size for the GPA in the sub-page control storage, if TLB entry has a sub-page protection indication;
invoking one or more microcode assist operations to perform fault checking if there is no match of the offset and/or operand size; and
caching write-permission bits for the GPA into a write-allowed scratchpad register when the one or more microcode assist operations are invoked.

8. The method as in claim 7 wherein if the GPA is not programmed in the sub-page control storage, then invoking one or more microcode assist operations to perform fault checking.

9. The method as in claim 7 wherein when the one or more microcode assist operations are invoked, the one or more microcode assist operations walk the sub-page protection table and programs the sub-page control storage with an offset and operand size if the sub-page protection table indicates that the offset accessed by an assisting store is writeable.

10. The method as in claim 9 wherein if the assisting store is not writeable, then an extended page table violation fault is triggered to notify a virtual machine monitor.

11. The method as in claim 7 wherein the sub-page control storage comprises a valid indication to indicate whether the data contained therein is valid, a GPA indication, an address operand size indication, and an address offset indication.

12. A system comprising:
a memory to store program code and data;
a processor to process the program code and data to implement a virtual machine monitor (VMM) and one or more guest operating systems (OSs) executed within one or more virtual machines (VMs) supported by the VMM, the guest OSs to utilize guest physical addresses (GPAs) to perform memory operations, the GPAs to be translated by the VMMs;
the processor further comprising:
a memory management unit implemented in a circuit, including a page miss handler to perform a page walk using a GPA and to detect, by checking one or more sub-page permission bits within a memory page table, whether a page identified with the GPA is mapped with the one or more sub-page permission bits that indicate walking a sub-page protection table being enabled for the page, and wherein the sub-page protection table indicates read and write permissions of sub-pages,
a sub-page control storage to store at least one GPA and other sub-page related data including an offset and operand size for the GPA; and
a write-allowed scratchpad register,
wherein the page miss handler is to determine whether the GPA is identified in the sub-page control storage, and
the page miss handler is to send a translation to a translation lookaside buffer (TLB) with a sub-page protection indication set to cause a matching of the sub-page related data when there is a TLB hit, the sub-page protection indication indicating the translation is for a sub-page TLB entry, wherein the TLB is further configured to match the offset and operand size for the GPA in the sub-page control storage, if a TLB entry with the sub-page protection indication was hit for an access, and wherein the TLB is to invoke one or more microcode assist operations to perform fault checking if there is no match of the offset and/or operand size when an access matches a TLB entry with sub-page protection indication, and
wherein when the one or more microcode assist operations are invoked by the page miss handler, the one or more microcode assist operations cache write-permission bits for the GPA into the write-allowed scratchpad register.

13. The system as in claim 12 wherein if the GPA is not programmed in the sub-page control storage, then the page miss handler to invoke one or more microcode assist operations t

Assignees

• Intel Corp

Inventors

• Shanbhogue Vedvyas
• Bryant Christopher
• Wiedemeier Jeff

Classifications

• G06F12/1045 Primary

  associated with a data cache · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F2212/452

  Instruction code · CPC title

• G06F2212/1024

  Latency reduction · CPC title