Decoding device and method using context redundancy

Patent metadata

Field	Value
Publication number	US-10255144-B2
Application number	US-201715611625-A
Country	US
Kind code	B2
Filing date	Jun 1, 2017
Priority date	Jul 18, 2016
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

The disclosure relates to a decoding device, comprising: a receiver configured to provide a sequence of information bits comprising context redundancy information, wherein the sequence of information bits is encoded based on a predefined channel code; a trellis generation logic configured to generate a plurality of trellis states based on the sequence of information bits and the channel code; a trellis reduction logic configured to reduce the plurality of trellis states by at least one trellis state based on the context redundancy information; and a decoder configured to decode the sequence of information bits by using a metric based on the reduced number of trellis states.

First claim

The invention claimed is:

1. A decoding device, comprising:
a receiver configured to provide a sequence of information bits comprising context redundancy information, wherein the sequence of information bits is encoded based on a predefined channel code;
a trellis generation logic configured to generate a plurality of trellis states based on the sequence of information bits and the channel code;
a trellis reduction logic configured to reduce a number of the plurality of trellis states by at least one trellis state based on the context redundancy information, wherein the trellis reduction logic is configured to provide the reduced number of the plurality of trellis states during an online operation of the decoding device, wherein the trellis reduction logic is configured to provide the reduced number of the plurality of trellis states based on evaluating probabilities for different possible context redundancy information; and
a decoder configured to decode the sequence of information bits by using a metric based on the reduced number of trellis states.

2. The decoding device of claim 1 ,
wherein the context redundancy information is provided at predefined positions of the sequence of information bits.

3. The decoding device of claim 1 ,
wherein the context redundancy information is provided as a bit field comprising at least one invalid bit combination.

4. The decoding device of claim 1 ,
wherein the sequence of information bits is correlated by the context redundancy information before being encoded based on the channel code.

5. The decoding device of claim 1 ,
wherein the trellis reduction logic is configured to remove trellis states which correspond to invalid bit allocations in the sequence of information bits.

6. The decoding device of claim 1 ,
wherein the trellis reduction logic is configured to remove trellis states which correspond to invalid field combinations in the sequence of information bits.

7. The decoding device of claim 1 ,
wherein the trellis reduction logic is configured to remove trellis states which are only reached by invalid paths.

8. The decoding device of claim 1 ,
wherein the trellis reduction logic is configured to provide the reduced number of trellis states based on trace back for decoding the context redundancy information.

9. The decoding device of claim 8 ,
wherein the trellis reduction logic is configured to use the decoded context redundancy information to restrict the plurality of trellis states.

10. The decoding device of claim 1 ,
wherein the trellis reduction logic is configured to provide the reduced number of trellis states based on evaluating hypotheses of different possible context redundancy information.

11. The decoding device of claim 10 ,
wherein the trellis reduction logic is configured to evaluate the hypotheses based on a cyclic redundancy check.

12. The decoding device of claim 1 ,
wherein the context redundancy information comprises at least one of self-context redundancy information and cross-context redundancy information.

13. The decoding device of claim 12 ,
wherein the self-context redundancy information comprises self-context redundancy of a bit field indicating a side link bandwidth within a sidelink master information block (SL-MIB) for device-to-device (D2D) communication.

14. The decoding device of claim 13 ,
wherein the cross-context redundancy information comprises cross-context redundancy between a bit field indicating a time division duplex uplink downlink (TDD-ULDL) configuration and the bit field indicating the side link bandwidth within the sidelink master information block (SL-MIB) for device-to-device (D2D) communication.

15. The decoding device of claim 1 ,
wherein the decoder is configured to decode the sequence of information bits based on Viterbi decoding.

16. A decoding method, comprising:
providing a sequence of information bits comprising context redundancy information, wherein the sequence of information bits is encoded based on a predefined channel code;
generating a plurality of trellis states based on the sequence of information bits and the channel code;
reducing a number of the plurality of trellis states by at least one trellis state based on the context redundancy information, wherein the reduced number of the plurality of trellis states are provided during an online operation of a decoding device, wherein the reduced number of the plurality of trellis states are provided based on evaluating probabilities for different possible context redundancy information; and
decoding the sequence of information bits by using a metric based on the reduced number of trellis states.

17. The decoding method of claim 16 ,
wherein the context redundancy information is provided at predefined positions of the sequence of information bits.

18. The decoding method of claim 16 ,
wherein the context redundancy information is provided as a bit field comprising at least one invalid bit combination.

19. The decoding method of claim 16 ,
wherein the sequence of information bits is correlated by the context redundancy information before being encoded by the channel code.

20. The decoding method of claim 16 , comprising:
removing trellis states which correspond to invalid bit allocations in the sequence of information bits.

21. A decoding method, comprising:
providing a sequence of information bits comprising self-context redundancy information and cross-context redundancy information, wherein the sequence of information bits is encoded based on a predefined channel code;
generating a plurality of trellis states based on the sequence of information bits and the channel code during offline processing;
reducing the plurality of trellis states by at least one trellis state based on the self-context redundancy information and the cross-context redundancy information during the offline processing; and
using the reduced plurality of trellis states for decoding a sequence of information bits during an online processing.

22. The decoding method of claim 21 , comprising:
providing the self-context redundancy information and the cross-context redundancy information at predefined positions of the sequence of information bits.

Assignees

• Intel Ip Corp

Inventors

• Eckardt Florian
• Yu Zhibin
• Xu Qing

Classifications

• H03M13/41

  using the Viterbi algorithm or Viterbi processors · CPC title

• H03M13/256

  with trellis coding, e.g. with convolutional codes and TCM · CPC title

• H04L1/0059

  Convolutional codes · CPC title

• H04L1/0054

  Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms · CPC title

• G06F11/1479

  Generic software techniques for error detection or fault masking · CPC title