Disaggregated memory appliance having a management processor that accepts request from a plurality of hosts for management, configuration and provisioning of memory

Patent metadata

Field	Value
Publication number	US-10254987-B2
Application number	US-201514867961-A
Country	US
Kind code	B2
Filing date	Sep 28, 2015
Priority date	Dec 12, 2013
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

Example embodiments provide a disaggregated memory appliance, comprising: a plurality of leaf memory switches that manage one or more memory channels of one or more of leaf memory modules; a low-latency memory switch that arbitrarily connects one or more external processors to the plurality of leaf memory modules over a host link; and a management processor that responds to requests from one or more external processors for management, maintenance, configuration and provisioning of the leaf memory modules within the memory appliance.

First claim

We claim:

1. A memory appliance, comprising:
a plurality of leaf memory switches that each manage one or more memory channels of one or more of leaf memory modules;
a low-latency memory switch that arbitrarily connects one or more external processors to the plurality of leaf memory modules over a host link; and
a management processor that responds to requests from one or more external processors for management, maintenance, configuration and provisioning of the leaf memory modules within the memory appliance but does not participate in movement of data except to access resources provisioned for the management processor;
wherein the management processor is implemented as part of a compute complex that enables multiple functions, including boot and initial configuration of the memory appliance, coordination of memory allocation for the one or more external processors, compute offloading, and setup of wormhole switching in which endpoints use target routing data supplied during a memory provisioning process to effect low-latency switching of memory data flits and metadata.

2. The memory appliance of claim 1 , further comprising: a plurality of leaf links that connect the low-latency memory switch to the plurality of leaf memory switches.

3. The memory appliance of claim 2 , wherein the management processor accepts and processes the requests from the one or more external processors for access to, or provisioning of, the leaf memory modules based on policy from a datacenter resource management service; and configures the leaf memory modules and leaf memory switches to satisfy requests for memory.

4. The memory appliance of claim 3 , wherein the management processor creates and maintains a configuration and allocation database to manage the leaf memory modules.

5. The memory appliance of claim 1 , wherein the management processor is coupled to other components of the compute complex, including a complex programmable logic device (CPLD), a network port, a voltage regulation component, a clock generator and distribution component, an EEPROM, a flash (BIOS) memory, and a solid-state drive.

6. The memory appliance of claim 1 , wherein the leaf memory switch comprises:
a leaf link PHY coupled to a leaf link layer controller; a low latency switch coupled to the leaf link controller; a lightweight memory controller and PHY pair for each memory channel coupled to the low latency switch; and wherein the management processor is coupled to low latency switch and the lightweight memory controllers.

7. The memory appliance of claim 1 , wherein the memory appliance uses a low-latency routing protocol used by both the low-latency memory switch and the leaf memory switches that encapsulate memory technology specific semantics by use of tags that uniquely identify the memory-technology during provisioning, monitoring and operation.

8. A method for providing a disaggregated memory appliance, comprising:
coupling a low-latency memory switch to a host link over which the low-latency memory switch receives requests and traffic from one or more external processors;
using a plurality of leaf links to connect the low-latency memory switch to a plurality of leaf memory switches that are connected to, and manage, one or more memory channels of one or more of leaf memory modules; and
responding, by a management processor, to the requests from the one or more external processors for management, maintenance, configuration and provisioning of the leaf memory modules within the memory appliance but not participating in movement of data except to access resources provisioned for the management processor;
wherein the management processor is implemented as part of a compute complex that enables multiple functions, including boot and initial configuration of the memory appliance, coordination of memory allocation for the one or more external processors, compute offloading, and setup of wormhole switching in which endpoints use target routing data supplied during a memory provisioning process to effect low-latency switching of memory data flits and metadata.

9. The method of claim 8 , further comprising:
accepting and processing, by the management processor, the requests for access to, or provisioning of, the leaf memory modules based on policy from a datacenter resource management service; and configuring the leaf memory modules and leaf memory switches to satisfy requests for memory.

10. The method of claim 9 , further comprising:
creating and maintaining, by the management processor, a configuration and allocation database to manage the leaf memory modules.

11. The method of claim 8 , further comprising:
coupling the management processor to other components of the compute complex, including a complex programmable logic device (CPLD), a network port, a voltage regulation component, a clock generator and distribution component, an EEPROM, a flash (BIOS) memory, and a solid-state drive.

12. The method of claim 8 , wherein the leaf memory switch comprises:
a leaf link PHY coupled to a leaf link layer controller; a low latency switch coupled to the leaf link controller; a lightweight memory controller and PHY pair for each memory channel coupled to the low latency switch; and wherein the management processor is coupled to low latency switch and the lightweight memory controllers.

13. The method of claim 8 , further comprising:
using a low-latency routing protocol by both the low-latency memory switch and the leaf memory switches that encapsulate memory technology specific semantics by use of tags that uniquely identify the memory-technology during provisioning, monitoring and operation.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Shrader Steven L
• Rogers Harry R
• Brennan Robert
• Shaeffer Ian P

Classifications

• G06F15/17312

  Routing techniques specific to parallel machines, e.g. wormhole, store and forward, shortest path problem congestion (routing on a LAN H04L45/00) · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0631

  by allocating resources to storage systems · CPC title

• G06F3/0611

  in relation to response time · CPC title