Data processing apparatus, controller, cache and method

Patent metadata

Field	Value
Publication number	US-10250709-B2
Application number	US-201615099244-A
Country	US
Kind code	B2
Filing date	Apr 14, 2016
Priority date	Apr 28, 2015
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

A data processing apparatus has multiple caches and a controller for controlling the caches. The controller and caches communicate over a first network and a second network. The first network is used for unicast communication from the controller to a specific one of the caches. The second network is used for communication of a multicast communication from the controller to two or more of the caches.

First claim

We claim:

1. A data processing apparatus comprising:
a plurality of caches;
a controller configured to control the plurality of caches;
a first network coupling the controller and the plurality of caches; and
a second network coupling the controller and the plurality of caches;
wherein the controller is configured to transmit a unicast communication to a specified one of the plurality of caches via the first network; and
the controller is configured to transmit a multicast communication to at least two of the plurality of caches via the second network,
wherein the multicast communication comprises a cache invalidation request for requesting invalidation of at least some data stored in said at least two caches, and wherein in response to a cache refill request received from a requesting cache of said plurality of caches via the first network, the cache refill request specifying target data to be provided in a cache refill response to the requesting cache via the first network, the controller is configured to initiate a line fill request to fetch the target data from a data store when the target data is not already available to the controller.

2. The data processing apparatus according to claim 1 , wherein the multicast communication comprises a broadcast communication to each of the plurality of caches.

3. The data processing apparatus according to claim 1 , wherein the first network comprises a switch network providing a plurality of communication paths between the controller and any given cache.

4. The data processing apparatus according to claim 1 , wherein the second network is configured to provide asynchronous communication between the controller and the plurality of caches.

5. The data processing apparatus according to claim 1 , wherein the unicast communication comprises a cache refill response providing data to be stored in said specified one of said plurality of caches.

6. The data processing apparatus according to claim 1 , wherein in response to the cache invalidation request, each of said at least two caches is configured to transmit a cache invalidation response to the controller via the second network.

7. The data processing apparatus according to claim 6 , wherein in response to detecting that each of said at least two caches has transmitted said cache invalidation response, the controller is configured to deassert the cache invalidation request.

8. The data processing apparatus according to claim 6 , wherein each of said at least two caches is configured to deassert the cache invalidation response when the cache has completed an invalidation process in response to the cache invalidation request.

9. The data processing apparatus according to claim 8 , wherein the controller is configured to defer issuing of a further cache invalidation request on the second network until each of said at least two caches has deasserted said cache invalidation response.

10. The data processing apparatus according to claim 6 , wherein at least one of said caches comprises response generating circuitry configured to generate the cache invalidation response in response to the cache invalidation request when the cache is in a power saving state.

11. The data processing apparatus according to claim 1 , wherein the multicast communication transmitted to the at least two caches via the second network also comprises identification information identifying which data is to be invalidated in response to said cache invalidation request.

12. The data processing apparatus according to claim 11 , wherein the identification information identifies at least one of:
an address or group of addresses of data to be invalidated;
an address space associated with data to be invalidated; and
a context associated with data to be invalidated.

13. The data processing apparatus according to claim 1 , wherein the controller is configured to transmit the cache invalidation request in response to receiving an invalidation control signal from another device.

14. The data processing apparatus according to claim 13 , wherein in response to the cache invalidation request, each of said at least two caches is configured to transmit a cache invalidation response to the controller via the second network; and
when, after transmission of the cache invalidation request, a further invalidation control signal is received from the other device, the controller is configured to suppress issuing of a further cache invalidation request in response to the further invalidation control signal if the cache invalidation response has not yet been received from each of the at least two caches.

15. The data processing apparatus according to claim 1 , wherein the controller is configured to discard target data fetched from the data store in response to at least one line fill request pending at the time of issuing the cache invalidation request.

16. The data processing apparatus according to claim 1 , wherein the controller is configured to provide the cache refill response in response to cache refill requests pending at the time of issuing the cache invalidation request.

17. The data processing apparatus according to claim 1 , wherein in response to the cache invalidation request, said at least two caches are configured to identify at least one outstanding cache refill request for which the cache refill response has not yet been provided by the controller, and to discard target data provided by the controller in response to said at least one outstanding cache refill request.

18. The data processing apparatus according to claim 17 , wherein in response to the cache invalidation request, said at least two caches are configured to reissue said at least one outstanding cache refill request to said controller.

19. The data processing apparatus according to claim 1 , wherein the plurality of caches comprise a plurality of translation lookaside buffers configured to store address translation data.

20. The data processing apparatus according to claim 1 , wherein the controller comprises a memory management unit.

21. A controller for controlling a plurality of caches of a data processing apparatus, comprising:
a first network interface configured to output a unicast communication to a specified one of the plurality of caches via a first network; and
a second network interface configured to output a multicast communication to at least two of the plurality of caches via a second network;
wherein the multicast communication comprises a cache invalidation request for requesting invalidation of at least some data stored in said at least two caches, and wherein in response to a cache refill request received from a requesting cache of said plurality of caches via the first network, the cache refill request specifying target data to be provided in a cache refill response to the requesting cache via the first network, the controller is configured to initiate a line fill request to fetch the target data from a data store when the target data is not already available to the controller.

22. A cache comprising:
a first network interface configured to receive a unicast communication from a controller via a first network, the unicast communication comprising a type of communication for which said cache is the only recipient; and
a second network interface configured to receive a multicast communication from the controller via a second network, the multicast communication comprising a type of communication for which recipients include said cache and at lea

Assignees

• Advanced Risc Mach Ltd

Inventors

• De Los Reyes Darias Jesus Javier
• Persson Hakan
• Grubisic Roko
• Pai Vinod Pisharath Hari

Classifications

• H04L12/5691

  Access to open networks; Ingress point selection, e.g. ISP selection · CPC title

• G06F12/0891

  using clearing, invalidating or resetting means · CPC title

• G06F12/0813 Primary

  with a network or matrix configuration · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• Y02D10/13

  Cross-Sectional Technologies · mapped topic