Clock synchronization

Patent metadata

Field	Value
Publication number	US-10250375-B2
Application number	US-201615273015-A
Country	US
Kind code	B2
Filing date	Sep 22, 2016
Priority date	Sep 22, 2016
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

An apparatus and a method are disclosed for synchronizing clock signals distributed within a wireless device. In some embodiments, a local oscillator (LO) clock signal is buffered and distributed to two or more transceivers within the wireless device. Each transceiver may include a configurable clock divider to divide the distributed LO clock signal and generate an output clock signal. A phase detector compares output clock signals from each of the configurable clock dividers and generates an output signal in accordance with a determined phase difference. The phase detector output signal may cause at least one of the configurable clock dividers to modify its respective output clock signal, and thereby synchronize output clock signals between different configurable clock dividers. In some embodiments, a clock signal from a configurable clock divider may be modified (shifted) by approximately 90 or 180 degrees.

First claim

What is claimed is:

1. An apparatus comprising:
a first circuit configured to:
generate a clock inhibit signal; and
generate a first clock divider reference signal and a second clock divider reference signal, wherein the first clock divider reference signal is phase offset with respect to the second clock divider reference signal and at least one cycle of the first clock divider reference signal and the second clock divider reference signal is inhibited when the clock inhibit signal is asserted; and

a second circuit configured to:
receive the first clock divider reference signal and the second clock divider reference signal;
select a clock signal from one of the first clock divider reference signal or the second clock divider reference signal based on a clock select signal; and
divide the selected clock signal in frequency to generate a divided clock signal, wherein the divided clock signal is based, at least in part, on the clock inhibit signal.

2. The apparatus of claim 1 , wherein the second circuit is configured to select one of the first clock divider reference signal or the second clock divider reference signal when the clock inhibit signal is asserted.

3. The apparatus of claim 2 , wherein the second circuit is further configured to select one of the first clock divider reference signal or the second clock divider reference signal based, at least in part, on a detected phase difference between a first reference signal and a second reference signal.

4. The apparatus of claim 3 , wherein the divided clock signal has at least one of an approximately 90 degree phase difference or an approximately 180 degree phase difference with respect to the first reference signal.

5. The apparatus of claim 4 , wherein the second reference signal is based, at least in part, on the divided clock signal.

6. The apparatus of claim 3 , wherein the first reference signal and the second reference signal are based, at least in part, on a local oscillator clock signal.

7. The apparatus of claim 1 , wherein the first clock divider reference signal and the second clock divider reference signal are gated clock signals each having at least one clock cycle inhibited based on the clock inhibit signal.

8. The apparatus of claim 1 , wherein the phase offset between the first clock divider reference signal and the second clock divider reference signal is approximately 180 degrees.

9. The apparatus of claim 1 , wherein the divided clock signal comprises an in-phase divided clock signal and a quadrature divided clock signal related by a phase-shift of approximately 90 degrees.

10. A method for synchronizing a first clock signal and a second clock signal, the method comprising:
generating a clock inhibit signal;
generating a first clock divider reference signal and a second clock divider reference signal, wherein the first clock divider reference signal is phase offset with respect to the second clock divider reference signal and at least one cycle of the first clock divider reference signal and the second clock divider reference signal is inhibited when the clock inhibit signal is asserted;
selecting a clock signal from one of the first clock divider reference signal or the second clock divider reference signal based on a clock select signal; and
dividing the selected clock signal in frequency thereby generating a divided clock signal, wherein the divided clock signal is based, at least in part, on the clock inhibit signal.

11. The method of claim 10 , further comprising:
selecting one of the first clock divider reference signal or the second clock divider reference signal when the clock inhibit signal is asserted.

12. The method of claim 11 , further comprising:
selecting one of the first clock divider reference signal or the second clock divider reference signal based, at least in part, on a detected phase difference between a first reference signal and a second reference signal.

13. The method of claim 12 , wherein the divided clock signal has at least one of an approximately 90 degree phase difference or an approximately 180 degree phase difference with respect to the first reference signal.

14. The method of claim 12 , wherein the second reference signal is based, at least in part, on the divided clock signal.

15. The method of claim 12 , wherein the first reference signal and the second reference signal are based, at least in part, on a local oscillator clock signal.

16. The method of claim 10 , wherein the first clock divider reference signal and the second clock divider reference signal are gated clock signals each having at least one clock cycle inhibited based on the clock inhibit signal.

17. An apparatus comprising:
means for generating a clock inhibit signal;
means for generating a first clock divider reference signal and a second clock divider reference signal, wherein the first clock divider reference signal is phase offset with respect to the second clock divider reference signal and at least one cycle of the first clock divider reference signal and the second clock divider reference signal is inhibited when the clock inhibit signal is asserted;
means for selecting a clock signal from one of the first clock divider reference signal or the second clock divider reference signal based on a clock select signal; and
means for dividing the selected clock signal in frequency thereby generating a divided clock signal, wherein the divided clock signal is based, at least in part, on the clock inhibit signal.

18. The apparatus of claim 17 , wherein the means for selecting the clock signal comprises:
selecting one of the first clock divider reference signal or a second clock divider reference signal when the clock inhibit signal is asserted.

19. The apparatus of claim 17 , wherein the means for selecting the clock signal comprises:
selecting one of the first clock divider reference signal or the second clock divider reference signal based, at least in part, on a detected phase difference between a first reference signal and a second reference signal.

20. The apparatus of claim 19 , wherein the divided clock signal has at least one of an approximately 90 degree phase difference or an approximately 180 degree phase difference with respect to the first reference signal.

21. The apparatus of claim 20 , wherein the second reference signal is based, at least in part, on the divided clock signal.

Assignees

• Qualcomm Inc

Inventors

• Black Justin
• Wang Cheng-Han
• Yang Jeongsik

Classifications

• H03J2200/11

  Cellular receiver, e.g. GSM, combined with a GPS receiver · CPC title

• H04W88/02

  Terminal devices · CPC title

• H03L7/143

  by switching the reference signal of the phase-locked loop · CPC title

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• H03L7/00

  Automatic control of frequency or phase; Synchronisation · CPC title