Asynchronous clock signal generator and semiconductor device for correcting multi-phase signals using asynchronous clock signal

Patent metadata

Field	Value
Publication number	US-10250243-B2
Application number	US-201715658272-A
Country	US
Kind code	B2
Filing date	Jul 24, 2017
Priority date	Dec 19, 2016
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

A semiconductor device includes a delay circuit configured to adjust a delay amount of multi-phase input signals to output multi-phase signals; a clock generator configured to output a clock signal that is not synchronized with an input signal which corresponds to one of the multi-phase signals; a detector circuit configured to generate a pulse signal corresponding to a phase difference between a reference signal corresponding to a predetermined one of the multi-phase signals and a comparison signal corresponding to a selected one of the multi-phase signals and to sample the pulse signal according to the clock signal; and a controller circuit configured to output a delay control signal for controlling a delay amount of the multi-phase input signals or controlling a delay amount of the comparison signal according to a result of calculating an output of the detector circuit and a reference value corresponding to the phase difference.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first delay circuit configured to adjust delay amounts of multi-phase input signals to output multi-phase signals;
a clock generator circuit configured to output a clock signal that is not synchronized with an input signal, the input signal corresponding to one of the multi-phase signals;
a detector circuit configured to generate a pulse signal corresponding to a phase difference between a reference signal corresponding to one of the multi-phase signals and a comparison signal corresponding to a selected one of the multi-phase signals, and to sample the pulse signal according to the clock signal; and
a controller circuit configured to output a delay control signal for controlling the delay amounts of the multi-phase input signals and controlling a delay amount of the comparison signal according to a result of calculating an output of the detector circuit and a reference value corresponding to the phase difference.

2. The semiconductor device of claim 1 , wherein the detector circuit comprises:
a first selector configured to select any one of the multi-phase signals according to a selection signal and to provide as the comparison signal;
a pulse generator circuit configured to generate a pulse signal corresponding to a phase difference between the reference signal and the comparison signal; and
a sampler circuit configured to sample the pulse signal according to the clock signal.

3. The semiconductor device of claim 2 , wherein the pulse generator circuit comprises:
a signal selector configured to output a first intermediate signal from the reference signal and to output a second intermediate signal from the comparison signal according to the selection signal; and
a pulse output circuit configured to output a pulse corresponding to a phase difference between the first intermediate signal and the second intermediate signal.

4. The semiconductor device of claim 3 , wherein when the reference signal and the comparison signal do not correspond to a same signal, the first intermediate signal is substantially identical to the reference signal, the second intermediate signal is substantially identical to the comparison signal, and the delay control signal controls an amount of delay of one of the multi-phase input signals, and
wherein when the reference signal and the comparison signal correspond to a same signal, the first intermediate signal has a period of K times of a period of the reference signal, wherein K is a natural number equal to or greater than 2, and has a pulse signal synchronized with a rising edge of the rising edges of the reference signal, the second intermediate signal has a period as same as a period of the first intermediate signal and has a pulse signal synchronized with a rising edge of the rising edges of the comparison signal, and the delay control signal controls an amount of delay of the comparison signal.

5. The semiconductor device of claim 2 , further comprising:
a second delay circuit configured to delay an output of the first selector and to output the comparison signal.

6. The semiconductor device of claim 1 , wherein the controller circuit comprises:
a calculation circuit configured to calculate a difference between the output of the detector circuit and the reference value; and
a loop filter circuit configured to increase or decrease the delay control signal according to an output of the calculation unit.

7. The semiconductor device of claim 6 , wherein the reference value corresponds to a ratio of the phase difference between the reference signal and the comparison signal and the period of the reference signal.

8. The semiconductor device of claim 7 , wherein the loop filter circuit increases the delay control signal by a first adjustment signal when the output from the calculation circuit is negative and the loop filter circuit decrease the delay control signal by a second adjustment signal when the output from the calculation circuit is positive.

9. The semiconductor device of claim 8 , wherein ratio of the first adjustment signal of the second adjustment signal corresponds to a ratio of the reference value and a value obtained by subtracting the reference value from 1.

10. The semiconductor device of claim 8 , wherein the loop filter circuit comprises:
a register configured to store a previous value of the delay control signal;
a fourth selector configured to output one of the first adjustment signal or a signal obtained by negating the second adjustment signal according to the output of the calculation circuit; and
an operation circuit configured to add the previous value of the delay control signal and the output of the fourth selector and to output the delay control signal.

11. The semiconductor device of claim 2 , further comprising:
a selection controller circuit configured to output the selection signal such that each of the multi-phase signals is sequentially selected according to the clock signal.

12. The semiconductor device of claim 11 , wherein the sampler circuit samples the pulse signal at a rising edge of the clock signal and the selection controller circuit operates synchronized with a falling edge of the clock signal.

13. The semiconductor device of claim 1 , wherein the clock generator circuit comprises:
a counter configured to count the input signal for one period of the clock signal;
a flip-flop configured to latch an output of the counter according to the clock signal;
a multiplier circuit configured to multiply the output of the flip-flop by M, where M is a natural number greater than 1;
a subtractor circuit configured to subtract N from an output of the multiplier circuit, where N is a natural number smaller than M, and M and N are relatively prime;
a digital filter circuit configured to filter an output of the subtractor circuit according to the clock signal; and
a digitally controlled oscillator configured to output the clock signal according to an output of the digital filter circuit.

14. The semiconductor device of claim 13 , wherein the counter is 1-bit counter and the counter is reset at a given time after a rising edge of the clock signal.

15. The semiconductor device of claim 13 , wherein the digital filter circuit comprises an accumulator circuit configured to accumulate the output of the subtractor circuit according to the clock signal.

16. The semiconductor device of claim 15 , wherein the flip-flop is configured to latch the output of the counter at the rising edge of the clock signal and the digital filter circuit is configured to accumulate the output of the subtractor circuit at the falling edge of the clock signal.

Assignees

• Sk Hynix Inc
• Korea Advanced Inst Sci & Tech

Inventors

• Lee Seonggyu
• Kim Yongjo
• Cho Seonghwan

Classifications

• H03K5/15033 Primary

  using a chain of bistable devices · CPC title

• H03K2005/00058

  controlled by a digital setting · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L7/1803

  the counter or frequency divider being connected to a cycle or pulse swallowing circuit · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title