Single-stage CMOS-based voltage quadrupler circuit

Patent metadata

Field	Value
Publication number	US-10250133-B2
Application number	US-201715652447-A
Country	US
Kind code	B2
Filing date	Jul 18, 2017
Priority date	Jul 18, 2017
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

A single stage voltage quadrupler circuit includes a first capacitive voltage boosting circuit responsive to a first clock signal and operable to boost a voltage at a first node in response to the first clock signal from a first voltage level to a second voltage level that is substantially two times the first voltage level. A pass transistor selectively passes the boosted voltage at the first node to a second node in response to a control signal generated by a bootstrapping capacitor circuit in response to the level shifted first clock signal. A second capacitive boosting circuit is operable to boost the voltage at the second node in response to a level shifted second clock signal that is the logical invert of the level shifted first clock signal to third voltage level that is substantially four times the first voltage level.

First claim

The invention claimed is:

1. A circuit, comprising:
a first transistor having a source-drain path coupled between a voltage input node and a first node;
a first boost capacitor having a first plate coupled to the first node and a second plate coupled to receive a first clock signal;
a first level shifting circuit configured to receive the first clock signal and output a level shifted first clock signal;
a second level shifting circuit configured to receive a second clock signal that is a logical invert of the first clock signal and output a level shifted second clock signal;
a second transistor having a source-drain path coupled between the voltage input node and a second node;
a first bootstrapping capacitor having a first plate coupled to the second node and a second plate coupled to receive the level shifted first clock signal;
a third transistor having a source-drain path coupled between the first node and a third node, said third transistor having a gate controlled by a first control signal at the second node; and
a second boost capacitor having a first plate coupled to the third node and a second plate coupled to receive the level shifted second clock signal;
wherein a gate of the first transistor and a gate of the second transistor are both driven by a second control signal.

2. The circuit of claim 1 , further comprising a first output transistor configured to selectively pass a voltage at the third node to an output voltage node.

3. The circuit of claim 2 , wherein the first, second and third transistors are of a first conductivity type and the first output transistor is of a second conductivity type opposite the first conductivity type.

4. The circuit of claim 1 , further comprising:
a fourth transistor having a source-drain path coupled between the voltage input node and a fourth node; and
a third boost capacitor having a first plate coupled to the fourth node and a second plate coupled to receive the second clock signal;
said second control signal generated at the fourth node.

5. The circuit of claim 4 , wherein a gate of the fourth transistor is driven by a third control signal generated at the first node.

6. The circuit of claim 4 , further comprising:
a fifth transistor having a source-drain path coupled between the voltage input node and a fifth node; and
a second bootstrapping capacitor having a first plate coupled to the fifth node and a second plate coupled to receive the level shifted second clock signal.

7. The circuit of claim 6 , wherein a gate of the fourth transistor and a gate of the fifth transistor are both driven by a third control signal generated at the first node.

8. The circuit of claim 6 , further comprising:
a sixth transistor having a source-drain path coupled between the fourth node and a sixth node, said sixth transistor having a gate controlled by a fourth control signal generated at the fifth node; and
a fourth boost capacitor having a first plate coupled to the sixth node and a second plate coupled to receive the level shifted first clock signal.

9. The circuit of claim 8 , further comprising:
a first output transistor configured to selectively pass a voltage at the third node to an output voltage node, said first output transistor having a gate driven by a fifth control signal generated at the sixth node; and
a second output transistor configured to selectively pass a voltage at the sixth node to the output voltage node, said second output transistor having a gate driven by a sixth control signal generated at the third node.

10. The circuit of claim 1 , wherein the first level shifting circuit comprises:
a first level shifter transistor having a source-drain path coupled between the first node and a level shifted first clock signal output node; and
a second level shifter transistor having a source-drain path coupled between the level shifted first clock signal output node and a node receiving the first clock signal.

11. The circuit of claim 10 , wherein gate terminals of the first and second level shifter transistors are both biased by a voltage at the voltage input node.

12. The circuit of claim 4 , wherein the second level shifting circuit comprises:
a first level shifter transistor having a source-drain path coupled between the fourth node and a level shifted second clock signal output node; and
a second level shifter transistor having a source-drain path coupled between the level shifted second clock signal output node and a node receiving the second clock signal.

13. The circuit of claim 12 , wherein gate terminals of the first and second level shifter transistors are both biased by a voltage at the voltage input node.

14. A circuit, comprising:
a first level shifting circuit configured to receive a first clock signal and output a level shifted first clock signal;
a second level shifting circuit configured to receive a second clock signal and output a level shifted second clock signal, wherein the second clock signal is a logical invert of the first clock signal;
a first voltage boosting circuit including a first capacitor having a first plate directly connected to a first node and a second plate coupled to receive the first clock signal, said first voltage boosting circuit configured to boost a voltage at the first node in response to the first clock signal from a first voltage level to a second voltage level that is substantially equal to two times the first voltage level;
a first pass transistor configured to selectively pass the boosted voltage at the first node to a second node in response to a first control signal generated in response to the level shifted first clock signal;
a second voltage boosting circuit including a second capacitor having a first plate directly connected to the second node and a second plate coupled to receive the level shifted second clock signal, said second voltage boosting circuit configured to boost a voltage at the second node in response to the level shifted second clock signal from the second voltage level to a third voltage level that is substantially equal to two times the second voltage level; and
a first control circuit configured to generate said first control signal, said first control circuit comprising:
a second transistor having a source-drain path coupled between the voltage input node and a third node, a gate of the second transistor controlled by said second control signal; and
a first bootstrapping capacitor having a first plate coupled to the third node and a second plate coupled to receive the level shifted first clock signal.

15. The circuit of claim 14 , wherein the first voltage boosting circuit further includes a first transistor having a source-drain path coupled between a voltage input node at the first voltage level and the first node, a gate of said first transistor controlled by a second control signal generated in response to the second clock signal.

16. The circuit of claim 14 , further comprising:
a third voltage boosting circuit including a third capacitor having a first plate directly connected to a fourth node and a second plate coupled to receive the second clock signal, said third voltage boosting circuit configured to boost a voltage at the fourth node in response to the second clock signal from the first voltage level to the second voltage level;
a second pass transistor configured to selectively pass the boosted voltage at the fourth node to a fifth node in response to a third control signal generated in response to the level shifted second clock signal; and
a fourth voltage boosting circuit including a fourth capacitor having a first pla

Assignees

• St Microelectronics Int Nv

Inventors

• Rana Vikas

Classifications

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H03K3/356104

  using complementary field-effect transistors (H03K3/35625 takes precedence) · CPC title

• H02M3/073

  Charge pumps of the Schenkel-type · CPC title