Memory device with plurality of interface connectors

Patent metadata

Field	Value
Publication number	US-10249970-B1
Application number	US-201815938436-A
Country	US
Kind code	B1
Filing date	Mar 28, 2018
Priority date	Sep 30, 2017
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

A memory device is provided. The memory device includes a substrate, a first interface connector, a second interface connector and a plurality of memory chips. The substrate includes a first edge, a second edge, a third edge and a fourth edge. The first interface connector is disposed on the first edge, wherein the first interface connector includes a plurality of first edge-board contacts, and the first edge-board contacts extend toward a first direction. The second interface connector is disposed on the second edge, the second interface connector includes a plurality of second edge-board contacts, and the second edge-board contacts extend toward a second direction. The memory chips are disposed on the substrate, wherein the second interface connector is located between the memory chips and the first interface connector in the first direction.

First claim

What is claimed is:

1. A memory device, comprising:
a substrate, which comprises a first edge, a second edge, a third edge and a fourth edge, wherein the first edge is parallel to the third edge, the second edge is parallel to the fourth edge, the first edge is perpendicular to the second edge, and a length of the first edge is shorter than a length of the second edge;
a first interface connector, disposed on the first edge, wherein the first interface connector comprises a plurality of first edge-board contacts, and the first edge-board contacts extend toward a first direction;
a second interface connector, disposed on the second edge, the second interface connector comprises a plurality of second edge-board contacts, and the second edge-board contacts extend toward a second direction; and
a plurality of memory chips, disposed on the substrate, wherein the second interface connector is located between the memory chips and the first interface connector in the first direction,
wherein the first interface connector is adapted to be inserted into a first interface slot, the second interface connector is adapted to be inserted into a second interface slot,
wherein the memory device is selectively connects to the first interface slot or the second interface slot.

2. The memory device as claimed in claim 1 , wherein the memory chips are arranged in the first direction.

3. The memory device as claimed in claim 2 , wherein the substrate comprises a first surface and a second surface, the first surface is opposite to the second surface, the memory chips comprise at least one first flash memory chip, and the first flash memory chip is disposed on the first surface.

4. The memory device as claimed in claim 3 , further comprising a controller, wherein the controller is disposed on the first surface of the substrate, the controller is located between the first flash memory chip and the second interface connector in the first direction.

5. The memory device as claimed in claim 4 , wherein the memory chips further comprise a DRAM chip, the DRAM chip is disposed on the first surface of the substrate, the DRAM chip is located between the first flash memory chip and the controller in the first direction.

6. The memory device as claimed in claim 5 , wherein the memory chips comprise a plurality of first flash memory chips, the first flash memory chips are disposed on the first surface and arranged in the first direction, the first flash memory chips are located between the DRAM chip and the third edge.

7. The memory device as claimed in claim 4 , further comprising at least one passive component, the passive component is located between the controller and the first interface connector in the first direction, and the passive component is located between the second interface connector and the fourth edge in the second direction.

8. The memory device as claimed in claim 7 , wherein the passive component is a capacitor.

9. The memory device as claimed in claim 4 , further comprising a plurality of passive components, the passive components are located between the controller and the first interface connector in the first direction, the passive components are located between the second interface connector and the fourth edge in the second direction, and the passive components are arranged in the first direction.

10. The memory device as claimed in claim 3 , wherein the memory chips comprise a plurality of second flash memory chips, and the second flash memory chips are disposed on the second surface and are arranged in the first direction.

11. The memory device as claimed in claim 10 , wherein the memory chips further comprise a DRAM chip, the DRAM chip is disposed on the second surface of the substrate, the DRAM chip and the second flash memory chip are arranged in the first direction.

12. The memory device as claimed in claim 1 , wherein the first interface connector is an M.2 connector, and the second interface connector is a PCIE connector.

13. The memory device as claimed in claim 1 , wherein the second interface connector has a connector height, the substrate has a substrate height, and the connector height is smaller than half of the substrate height.

14. The memory device as claimed in claim 1 , wherein the substrate is equally compartmentalized into an upper substrate part and a lower substrate part in the second direction, and the second interface connector is only located in the lower substrate part.

Assignees

• Silicon Motion Inc

Inventors

• Lin Sheng-Liu

Classifications

• H05K1/029

  having a programmable lay-out, i.e. adapted for choosing between a few possibilities · CPC title

• H05K1/117 Primary

  Pads along the edge of rigid circuit boards, e.g. for pluggable connectors · CPC title

• G11C11/005

  comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells · CPC title

• H05K2201/10015

  Non-printed capacitor · CPC title

• H01R12/7076

  for connection between PCB and component, e.g. display · CPC title