Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10249749-B2
Application number	US-201815997856-A
Country	US
Kind code	B2
Filing date	Jun 5, 2018
Priority date	Jun 6, 2017
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

A semiconductor device includes a buffer layer, a channel layer, and a carrier supply layer; first and second recesses formed in the channel layer and the carrier supply layer, to reach the buffer layer; first and second nitride semiconductor layers in the first and second recess, respectively; a source electrode over the first nitride semiconductor layer; a drain electrode over the second nitride semiconductor layer; and a gate electrode over the carrier supply layer between the first and second recesses. Each of the first and second nitride semiconductor layers includes first and second regions containing donors. An interface between the first and second regions is positioned deeper than two-dimensional electron gas on a surface side of the channel layer, and energy at a bottom of a conduction band of the second region is higher than energy at a bottom of a conduction band of the first region.

First claim

What is claimed is:

1. A semiconductor device comprising:
a buffer layer;
a channel layer over the buffer layer;
a carrier supply layer over the channel layer;
a first recess and a second recess that are formed in the channel layer and the carrier supply layer, and that reach the buffer layer;
a first nitride semiconductor layer in the first recess;
a second nitride semiconductor layer in the second recess;
a source electrode over the first nitride semiconductor layer;
a drain electrode over the second nitride semiconductor layer; and
a gate electrode over the carrier supply layer between the first recess and the second recess,
wherein each of the first nitride semiconductor layer and the second nitride semiconductor layer includes
a first region containing donors, and
a second region under the first region,
wherein an interface between the first region and the second region is positioned deeper than two-dimensional electron gas on a surface side of the channel layer, and
wherein energy at a bottom of a conduction band of the second region is higher than energy at a bottom of a conduction band of the first region.

2. The semiconductor device as claimed in claim 1 , further comprising:
a back barrier layer between the buffer layer and the channel layer.

3. The semiconductor device as claimed in claim 2 , wherein the back barrier layer includes In at a higher concentration than the channel layer.

4. The semiconductor device as claimed in claim 2 , wherein the back barrier layer contacts the second region.

5. The semiconductor device as claimed in claim 1 , wherein the second region is of i-type.

6. The semiconductor device as claimed in claim 5 , wherein the first region includes an n-type GaN, and the second region includes an i-type GaN.

7. The semiconductor device as claimed in claim 1 , wherein each of the first nitride semiconductor layer and the second nitride semiconductor layer includes a third region containing donors under the second region.

8. The semiconductor device as claimed in claim 7 , wherein the third region includes an n-type GaN.

9. The semiconductor device as claimed in claim 1 , wherein a band gap of the second region is greater than a band gap of the buffer layer.

10. The semiconductor device as claimed in claim 9 , wherein the first region includes an n-type GaN, and the second region includes AlGaN.

11. The semiconductor device as claimed in claim 1 , wherein the carrier supply layer includes In and Al.

12. The semiconductor device as claimed in claim 1 , wherein the first region includes Si as donors at a concentration of 1×10 19 cm −3 or greater.

13. A method of manufacturing a semiconductor device, the method comprising:
a process of forming a channel layer over a buffer layer;
a process of forming a carrier supply layer over the channel layer;
a process of forming a first recess and a second recess that reach the buffer layer, in the channel layer and the carrier supply layer;
a process of forming a first nitride semiconductor layer in the first recess, and forming a second nitride semiconductor layer in the second recess;
a process of forming a source electrode over the first nitride semiconductor layer, and forming a drain electrode over the second nitride semiconductor layer;
a process of forming a gate electrode over the carrier supply layer between the first recess and the second recess,
wherein the process of forming the first nitride semiconductor layer and the second nitride semiconductor layer includes
a process of forming a second region, and
a process of forming a first region containing donors over the second region,
wherein an interface between the first region and the second region is positioned deeper than two-dimensional electron gas on a surface side of the channel layer, and
wherein energy at a bottom of a conduction band of the second region is higher than energy at a bottom of a conduction band of the first region.

Assignees

• Fujitsu Ltd

Inventors

• Makiyama Kozo

Classifications

• H01L29/0843

  Electricity · mapped topic

• H01L29/2003

  Electricity · mapped topic

• H01L29/80

  Electricity · mapped topic

• H01L29/7784 Primary

  Electricity · mapped topic

• H01L29/66462

  Electricity · mapped topic