Thermal management of selector

Patent metadata

Field	Value
Publication number	US-10249680-B2
Application number	US-201815874977-A
Country	US
Kind code	B2
Filing date	Jan 19, 2018
Priority date	Jul 27, 2016
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

A non-volatile memory device that limits the temperature excursion of a selector during operation to enhance the cycling life of the non-volatile memory device. A selector, in line with a memory element, may be degraded with repeated temperature excursions as current passes through a stack during the read/write process. The selector changes from an amorphous state to become crystalline thus reducing the life of a memory device. The memory device includes a word line, a bit line disposed perpendicular to the word line, a stack—including a memory element, a selector, and a spacer—disposed between the word line and bit line, and one or more insulating layers surrounding an outer surface of the stack disposed between the word line and bit line. By surrounding the selector with a high thermal conductive heat-sink material, heat is directed away from the selector helping maintain the selector's amorphous state longer.

First claim

What is claimed is:

1. A memory device, comprising:
a word line;
a bit line disposed perpendicular to the word line; and
a stack disposed between the word line and the bit line, wherein the stack comprises:
a memory element;
a selector having a plurality of sides, wherein the selector comprises alternating layers of selector elements and heat sinks;
a spacer layer disposed between the memory element and the selector;
a first insulating layer disposed between the word line and the bit line;
a second insulating layer disposed in direct contact with the first insulating layer; and
a dissipation layer disposed in direct contact with the first insulating layer;

wherein the dissipation layer is adjacent to the second insulating layer and a same width as the second insulating layer.

2. The memory device of claim 1 , wherein the selector further comprises an insulating layer surrounding the alternating layers of selector elements and heat sinks.

3. The memory device of claim 2 , wherein the stack further comprises:
electrode contacts; and
barriers.

4. The memory device of claim 1 , further comprising an insulating layer surrounding the stack.

5. The memory device of claim 1 , wherein the heat sinks comprise:
a first electromigration barrier;
a heat sink element disposed on the first electromigration barrier; and
a second electromigration barrier disposed on the heat sink element.

6. The memory device of claim 5 , wherein the first electromigration barrier and the second electromigration barrier include at least one of cobalt and nickel.

7. The memory device of claim 1 , wherein the selector is selected from the group consisting of an ovonic threshold switch, a doped-chalcogenide alloy, thin film Si, an ovonic threshold switch thin film selector, an ovonic memory switch, a metal/metal-oxide switch, a field effector transistor, a bipolar junction transistor, and a diode.

8. The memory device of claim 1 , wherein the memory element is phase change memory.

9. A memory device, comprising:
a word line;
a bit line disposed perpendicular to the word line; and
a stack disposed between the word line and the bit line, wherein the stack comprises:
a memory element;
a selector having a plurality of sides, wherein the selector comprises alternating layers of selector elements and heat sinks; and
a spacer layer disposed between the memory element and the selector, wherein the selector further comprises an insulating layer surrounding the alternating layers of selector elements and heat sinks, wherein the stack further comprises:
electrode contacts; and
barriers, wherein the stack comprises:
a first barrier of the barriers disposed on the bit line;
a first electrode contact of the electrode contacts disposed on the first barrier;
the selector disposed on the first electrode contact;
a second electrode contact of the electrode contacts disposed on the selector; and
a second barrier of the barriers disposed on the second electrode contact.

10. The memory device of claim 9 , where the stack further comprises:
the spacer layer disposed on the second barrier;
a third electrode contact of the electrode contacts disposed on the spacer layer;
the memory element disposed on the third electrode contact; and
a fourth electrode contact of the electrode contacts disposed on the memory element.

11. The memory device of claim 10 , wherein the word line is disposed on the fourth electrode contact.

12. The memory device of claim 11 , further comprising an insulating layer surrounding the stack.

13. The memory device of claim 12 , wherein the heat sinks comprise:
a first electromigration barrier;
a heat sink element disposed on the first electromigration barrier; and
a second electromigration barrier disposed on the heat sink element.

14. The memory device of claim 13 , wherein the first electromigration barrier and the second electromigration barrier include at least one of cobalt and nickel.

15. The memory device of claim 14 , wherein the memory element is phase change memory.

16. A memory device, comprising:
a word line;
a bit line disposed perpendicular to the word line; and
a stack disposed between the word line and the bit line, wherein the stack comprises:
a memory element;
a selector having a plurality of sides, wherein the selector comprises alternating layers of selector elements and heat sinks; and
a spacer layer disposed between the memory element and the selector, wherein the stack comprises:
a first barrier disposed on the bit line;
a first electrode contact disposed on the first barrier;
the selector disposed on the first electrode contact;
a second electrode contact disposed on the selector; and
a second barrier disposed on the second electrode contact.

17. The memory device of claim 16 , where the stack further comprises:
the spacer layer disposed on the second barrier;
a third electrode contact disposed on the spacer layer;
the memory element disposed on the third electrode contact; and
a fourth electrode contact disposed on the memory element.

18. The memory device of claim 17 , wherein the word line is disposed on the fourth electrode contact.

19. A memory device, comprising:
a word line;
a bit line disposed perpendicular to the word line; and
a stack disposed between the word line and the bit line, wherein the stack comprises:
a first insulating layer disposed between the word line and the bit line;
a second insulating layer disposed in direct contact with the first insulating layer; and
a dissipation layer disposed in direct contact with the first insulating layer;

wherein the dissipation layer is adjacent to the second insulating layer and a same width as the second insulating layer;
a selector element; and

means to direct heat away from the selector.

20. The memory device of claim 19 , further comprising means to prevent electromigration.

Assignees

• Western Digital Tech Inc

Inventors

• Apodaca Mac D
• Rubin Kurt Allan

Classifications

• H01L45/141

  Electricity · mapped topic

• H01L27/2409 Primary

  Electricity · mapped topic

• H01L45/085

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic

• H01L27/2436

  Electricity · mapped topic