Split-gate conditional-reset image sensor

Patent metadata

Field	Value
Publication number	US-10249660-B2
Application number	US-201414898054-A
Country	US
Kind code	B2
Filing date	Jun 9, 2014
Priority date	Jun 11, 2013
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

In a pixel array within an integrated-circuit image sensor, a pixel ( 870 ) includes a photodetector ( 260 ) and floating diffusion ( 262 ) formed within a substrate. First ( 881 ) and second ( 883 ) gate elements are disposed adjacent one another over a region ( 885 ) of the substrate between the photodetector and the floating diffusion and coupled respectively to a row line (TGr) that extends in a row direction within the pixel array and a column line (TGc) that extends in a column direction within the pixel array.

First claim

What is claimed is:

1. An integrated-circuit image sensor, comprising a pixel array having:
a first photodetector formed within a substrate;
a floating diffusion formed within the substrate;
first and second gate elements disposed adjacent one another over a first charge transfer region of the substrate between the first photodetector and the floating diffusion, the first and second gate elements respectively controlling first and second serial sections of the first charge transfer region;
a first row line extending in a row direction within the pixel array and coupled to the first gate element;
a first column line extending in a column direction within the pixel array and coupled to the second gate element; and
circuitry to detect a level of photocharge integrated within the first photodetector and to conditionally assert a control pulse on the first column line according to whether the level of photocharge exceeds a threshold.

2. The integrated-circuit image sensor of claim 1 , the pixel array further comprising:
a second photodetector formed within the substrate;
third and fourth gate elements disposed adjacent one another over a second charge transfer region of the substrate between the second photodetector and the floating diffusion, the third and fourth gate elements respectively controlling third and fourth serial sections of the second charge transfer region, the third gate element being coupled to the first row line; and
a second column line extending in a column direction within the pixel array and coupled to the fourth gate element.

3. The integrated-circuit image sensor of claim 2 wherein the first and third gate elements are formed by a continuous conductive feature.

4. The integrated-circuit image sensor of claim 2 wherein the first photodetector and second photodetector are constituents of respective pixels within a first row of pixels.

5. The integrated-circuit image sensor of claim 4 , the pixel array further comprising:
a third photodetector formed within the substrate;
fifth and sixth gate elements disposed adjacent one another over a third charge transfer region of the substrate between the third photodetector and the floating diffusion, the fifth and sixth gate elements respectively controlling fifth and sixth serial sections of the third charge transfer region, the sixth gate element being coupled to the first column line; and
a second row line extending in a row direction within the pixel array and coupled to the fifth gate element.

6. The integrated-circuit image sensor of claim 5 wherein the second and sixth gate elements are formed by a continuous conductive feature.

7. The integrated-circuit image sensor of claim 5 wherein the first photodetector and third photodetector are constituents of respective pixels within a first column of pixels.

8. The integrated-circuit image sensor of claim 1 wherein the first gate element is disposed over the first charge transfer region nearer the first photodetector than the second gate element and the second gate element is disposed over the first charge transfer region nearer the floating diffusion than the first gate element.

9. The integrated-circuit image sensor of claim 1 wherein a spacing between the first and second gate elements is less than a minimum distance specified for implementing a source/drain implant between gate terminals of adjacent transistors under a fabrication process employed to fabricate the integrated-circuit image sensor.

10. The integrated-circuit image sensor of claim 1 wherein the first and second gate elements constitute field-effect gate elements such that, when row and column control signals are asserted on the first row line and first column line, respectively, overlapping electrostatic fields are formed within the first charge transfer region, the overlapping electrostatic fields effecting formation of a charge-conducting channel within the first charge transfer region.

11. The integrated-circuit image sensor of claim 10 further comprising row circuitry to assert, as at least part of the row control signal on the first row line, a partial-transfer pulse at a first time and a full-transfer pulse at a second time, the partial-transfer pulse enabling a partial transfer of charge from the first photodetector to the floating diffusion if charge accumulated within the first photodetector exceeds a threshold level, and the full-transfer pulse conditionally enabling a full transfer of charge from the first photodetector to the floating diffusion, the full transfer of charge effecting a reset of the photodetector.

12. The integrated-circuit image sensor of claim 11 wherein the partial-transfer pulse and full transfer pulse differ from one another in respect to at least one of amplitude or duration.

13. An integrated circuit image sensor comprising:
a substrate;
a plurality of row control signal lines and a plurality of column control signal lines;
a plurality of photosensitive elements disposed within the substrate to accumulate charge in response to incident light;
a shared floating diffusion disposed within the substrate to enable read-out of each of the photosensitive elements; and
a plurality of dual-control transfer gates each disposed over a region of the substrate between a respective one of the photosensitive elements and the shared floating diffusion, each of the dual-control transfer gates including first and second gate elements controlled by a respective unique combination of one of the row control signal lines and one of the column control signal lines.

14. The integrated circuit image sensor of claim 13 wherein the first and second gate elements constitute field-effect gate elements such that, when first and second control signals are asserted concurrently on the respective unique combination of control signal lines, overlapping electrostatic fields are formed within the region of the substrate between the respective one of the photosensitive elements and the floating diffusion, the overlapping electrostatic fields effecting formation of a charge-conducting channel within the region of the substrate between the respective one of the photosensitive elements and the floating diffusion that enables charge accumulated within the one of the photosensitive elements to be transferred to the shared floating diffusion.

15. The integrated circuit image sensor of claim 13 further comprising control circuitry to concurrently assert control signals on the respective unique combination of control signal lines during a first interval to enable determination of whether charge accumulated within the one of the photosensitive elements during integration interval exceeds a first threshold.

16. The integrated circuit image sensor of claim 15 wherein the control circuitry further comprising circuitry to concurrently assert control signals on the respective unique combination of control signal lines during a second interval if the first threshold is determined to be exceeded, wherein concurrent assertion of control signals on the control signal lines during the second interval enables generation of a read-out signal corresponding to a level of charge accumulated within the one of the photosensitive elements during the integration interval.

17. The integrated circuit image sensor of claim 15 wherein, in addition to enabling generation of the read-out signal, concurrent assertion of control signals on the respective unique combination of control signal lines resets the one of the photosensitive elements to an initial state in preparation for subsequent charge integration within th

Assignees

• Rambus Inc

Inventors

• Guidash Michael
• Vogelsang Thomas

Classifications

• H04N25/46

  by combining or binning pixels · CPC title

• H04N25/778

  comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself · CPC title

• H04N25/583

  with different integration times · CPC title

• H01L27/14643

  Electricity · mapped topic

• H01L27/14614 Primary

  Electricity · mapped topic