Thin film transistor array substrate and display panel

Patent metadata

Field	Value
Publication number	US-10249649-B2
Application number	US-201715563637-A
Country	US
Kind code	B2
Filing date	Apr 18, 2017
Priority date	Mar 10, 2017
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

A thin film transistor array substrate and a display panel are provided. A parasitic capacitor is formed from a common line and a data line, and a capacitance value of the parasitic capacitor formed from the data line connected to the connecting line with a larger resistance value and the corresponding common line is less than that of the parasitic capacitor formed from the data line connected to the connecting line with a smaller resistance value and the corresponding common line. Thus the displayed image bright stripes with inconsistent brightness can be avoided from appearing.

First claim

What is claimed is:

1. A thin film transistor array substrate, comprising:
a plurality of fan-out areas located in a non-display area of the thin film transistor array substrate, wherein a display area of the thin film transistor array substrate has a plurality of sub display areas corresponding to the fan-out areas respectively, and the sub display areas and the fan-out areas are arranged opposite each other;
a plurality of scanning lines extended along a first direction;
a plurality of data line combinations comprising a plurality of data lines extended along a second direction, wherein the first direction and the second direction are orthogonal to each other;
a plurality of common line combinations comprising a plurality of common lines crossing with the data lines, wherein a parasitic capacitor is formed on an overlapping area of the common line and the data line; and
a plurality of connecting line combinations, each of which is located in one of the fan-out areas, wherein the connecting line combinations comprise a plurality of connecting lines connecting to the data lines;
wherein a capacitance value of the parasitic capacitor formed from the data line connected to the connecting line with a larger resistance value and the corresponding common line is less than that of the parasitic capacitor formed from the data line connected to the connecting line with a smaller resistance value and the corresponding common line;
wherein the resistance value of the connecting line is gradually increased from an intermediate area of the fan-out area to two sides of the fan-out area;
wherein the connecting line located in the intermediate area of the fan-out area connects to the data line located in an intermediate area of the sub display area, and the connecting line located at the two sides of the fan-out area connects to the data line located at the two sides of the sub display area;
wherein a capacitance value of the parasitic capacitors formed from the data line combination and the common line combination are reduced from the intermediate area of the sub display area to the two sides of the sub display area;
wherein the common line comprises:
a first sub line being parallel to the data line; and
at least one second sub line being parallel to the scanning line;
wherein the second sub line and the scanning line are formed from a first metal layer, the first sub line and the data line are formed from a second metal layer, the first sub line and the second sub line are connected by a through hole, and the through hole is disposed through an insulating layer between the scanning line and the data line; and
wherein the parasitic capacitor is formed from the data line and the second sub line of the common line.

2. The thin film transistor array substrate according to claim 1 , wherein the connecting line combination comprises a first connecting line, a second connecting line, and a third connecting line; the data line combination comprises a first data line, a second data line, and a third data line; and the common line combination comprises a first common line, a second common line, and a third common line;
wherein the first connecting line is located the intermediate area of the fan-out area, and the second connecting line and the third connecting line are located at the two sides of the fan-out area respectively;
wherein the first data line and the first common line are located in the intermediate area of the sub display area, the second data line and the second common line are located at one side of the sub display area, and the third data line and the third common line are located at the other side of the sub display area;
wherein the first data line connects to the first connecting line, the second data line connects to the second connecting line, and the third data line connects to the third connecting line; and
wherein a first capacitance value of a first parasitic capacitor formed from the first common line and the first data line matches with a first resistance value of the first connecting line, a second capacitance value of a second parasitic capacitor formed from the second common line and the second data line matches with a second resistance value of the second connecting one, and a third capacitance value of a third parasitic capacitor formed from the third common line and the third data line matches with a third resistance value of the third connecting line.

3. The thin film transistor array substrate according to claim 1 , wherein a resistance value of the connecting line located in the intermediate area of the fan-out area is less than that of the connecting line located at the two sides of the fan-out area, a capacitance value of a parasitic capacitor located in the intermediate area of the sub display area is greater than that of a parasitic capacitor located at the two sides of the sub display area.

4. The thin film transistor array substrate according to claim 1 , wherein a resistance value of the connecting line is gradually increased from the intermediate area of the fan-out area to the two sides of the fan-out area; and
wherein an overlapping area of the common line and the data line connected the connecting line is reduced from the intermediate area of the sub display area to the two sides of the sub display area.

5. The thin film transistor array substrate according to claim 1 , wherein a resistance value of the connecting line is gradually increased from the intermediate area of the fan-out area to the two sides of the fan-out area; and
wherein a thickness of the insulating layer between the common line and the data line connected the connecting line is gradually increased from the intermediate area of the sub display area to the two sides of the sub display area.

6. A thin film transistor array substrate, comprising:
a plurality of fan-out areas located in a non-display area of the thin film transistor array substrate, wherein a display area of the thin film transistor array substrate has a plurality of sub display areas corresponding to the fan-out areas respectively, and the sub display areas and the fan-out areas are arranged opposite each other;
a plurality of scanning line extended along a first direction;
a plurality of data line combinations comprising a plurality of data lines extended along a second direction, wherein the first direction and the second direction are orthogonal to each other;
a plurality of common line combinations comprising a plurality of common lines crossing with the data lines, wherein a parasitic capacitor is formed on an overlapping area of the common line and the data line; and
a plurality of connecting line combinations, each of which is located in one of the fan-out areas, wherein the connecting line combinations comprise a plurality of connecting lines connecting to the data lines;
wherein a capacitance value of the parasitic capacitor formed from the data line connected to the connecting line with a larger resistance value and the corresponding common line is less than that of the parasitic capacitor formed from the data line connected to the connecting line with a smaller resistance value and the corresponding common line.

7. The thin film transistor array substrate according to claim 6 , wherein a resistance value of the connecting line is gradually increased from the intermediate area of the fan-out area to two sides of the fan-out area; and
wherein the connecting line located in the intermediate area of the fan-out area connects to the data line located in an intermediate area of the sub display area, and the connecting line located at the two sides of the fan-out area connects to the data line located at the two sides of the sub display area;
wherein a capacitance value of the parasitic capacit

Assignees

• Shenzhen China Star Optoelect

Inventors

• An Liyang

Classifications

• G09G2320/0223

  Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes · CPC title

• H01L27/3276

  Electricity · mapped topic

• G09G3/36

  using liquid crystals · CPC title

• H01L29/786

  Electricity · mapped topic

• H01L27/124 Primary

  Electricity · mapped topic