Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10249604-B2
Application number	US-201514656298-A
Country	US
Kind code	B2
Filing date	Mar 12, 2015
Priority date	Aug 13, 2014
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

A semiconductor device includes a base substrate and a semiconductor chip on the base substrate, the semiconductor chip including a first layer structure and a second layer structure opposite to the first layer structure, at least one of the first and second layer structures including a semiconductor device portion, and a bonding structure between the first layer structure and the second layer structure, the bonding structure including a silver-tin (Ag—Sn) compound and a nickel-tin (Ni—Sn) compound.

First claim

What is claimed is:

1. A semiconductor device comprising:
a base substrate; and
a semiconductor chip on the base substrate, the semiconductor chip being an individual semiconductor chip, the semiconductor chip including:
a first layer structure and a second layer structure opposite to the first layer structure, the second layer structures is a semiconductor device portion, and
a bonding structure between the first layer structure and the second layer structure, the bonding structure including a silver-tin (Ag—Sn) compound portion and a nickel-tin (Ni—Sn) compound portion above and below the Ag—Sn compound portion, the Ag—Sn compound portion and the Ni—Sn compound portion having a same width in a horizontal direction such that edge portions of the Ag—Sn compound portion are exposed and edge portions of the Ni—Sn compound portion are exposed,

wherein the first layer structure is a chip substrate including a semiconductor substrate,
wherein the chip substrate including the semiconductor substrate is between the base substrate and the semiconductor device portion, and
wherein the individual semiconductor chip includes the chip substrate, the semiconductor device portion and the bonding structure between the chip substrate and the semiconductor device portion.

2. The semiconductor device of claim 1 , wherein the bonding structure further includes pure Ni.

3. The semiconductor device of claim 1 , wherein
the Ag—Sn compound portion includes Ag 3 Sn, and
the Ni—Sn compound portion includes Ni 3 Sn 4 .

4. The semiconductor device of claim 3 , wherein the bonding structure includes
an intermediate layer including the Ag 3 Sn portion and the Ni 3 Sn 4 portion,
a first Ni layer between the intermediate layer and the first layer structure, and
a second Ni layer between the intermediate layer and the second layer structure.

5. The semiconductor device of claim 3 , wherein the Ni—Sn compound portion further includes Ni 3 Sn.

6. The semiconductor device of claim 1 , wherein an Ag content in the bonding structure is about 0.5 wt % to about 23.1 wt %.

7. The semiconductor device of claim 1 , wherein the semiconductor device portion includes a light-emitting device portion.

8. The semiconductor device of claim 7 , wherein
the first layer structure includes a silicon (Si) substrate,
the second layer structure includes the light-emitting device portion, and
the light-emitting device portion includes a Group III-V semiconductor.

9. The semiconductor device of claim 1 , wherein
the first layer structure includes a first substrate and a first semiconductor device portion on the first substrate, and
the second layer structure includes a second substrate and a second semiconductor device portion on the second substrate.

10. The semiconductor device of claim 1 , wherein at least one third layer structure is bonded onto the second layer structure.

11. The semiconductor device of claim 1 , wherein a die shear strength of the bonding structure is 32 MPa or more.

12. The semiconductor device of claim 1 , wherein a re-melting temperature of the bonding structure is 350 deg. C. or more.

13. The semiconductor device of claim 1 , wherein an average elastic modulus of both the Ag—Sn compound portion and the Ni—Sn compound portion is 124 GPa to 152 GPa.

14. The semiconductor device of claim 1 , wherein an average hardness of both the Ag—Sn compound portion and the Ni—Sn compound portion is 4.5 GPa to 9 GPa as measured by a Vickers hardness scale.

15. A semiconductor chip, the semiconductor chip comprising:
a bonding layer between a first layer structure and a second layer structure, the bonding layer including a silver-tin (Ag—Sn) compound portion and a nickel-tin (Ni—Sn) compound portion above and below the Ag—Sn compound portion, the Ag—Sn compound portion and the Ni—Sn compound portion having a same width in a horizontal direction such that edge portions of the Ag—Sn compound portion are exposed and edge portions of the Ni—Sn compound portion are exposed,
wherein the semiconductor chip is an individual semiconductor chip,
wherein the first layer structure is a chip substrate including a semiconductor substrate, and the second layer structure is a semiconductor device portion, and
wherein the individual semiconductor chip includes the chip substrate, the semiconductor device portion and the bonding layer between the chip substrate and the semiconductor device portion.

16. The semiconductor chip of claim 15 , wherein
the Ag—Sn compound portion includes Ag 3 Sn, and
the Ni—Sn compound portion includes Ni 3 Sn 4 .

17. The semiconductor chip of claim 16 , wherein the Ni—Sn compound portion further includes Ni 3 Sn.

18. The semiconductor chip of claim 16 , wherein the bonding layer includes
an intermediate layer including the Ag 3 Sn portion and the Ni 3 Sn 4 portion,
a first layer on a first side of the intermediate layer, the first layer including pure Ni, and
a second layer on a second side of the intermediate layer, the second layer including pure Ni.

19. The semiconductor chip of claim 15 , wherein an Ag content in the bonding layer is about 0.5 wt % to about 23.1 wt %.

20. The semiconductor chip of claim 15 , wherein
the first layer structure includes a first substrate and a first semiconductor device portion on the first substrate, and
the second layer structure includes a second substrate and a second semiconductor device portion on the second substrate.

21. A semiconductor device comprising:
a base substrate;
a semiconductor chip on the base substrate, the semiconductor chip being an individual semiconductor chip, the semiconductor chip including:
a first layer structure and a second layer structure opposite to the first layer structure, at least one of the first and second layer structures including a semiconductor device portion, and
a bonding structure between the first layer structure and the second layer structure, the bonding structure including a silver-tin (Ag—Sn) compound portion and a nickel-tin (Ni—Sn) compound portion above and below the Ag—Sn compound portion; and

a filling material between the base substrate and the semiconductor chip,
wherein the bonding structure is spaced apart from the filling material and no portion of the bonding structure contacts the filling material;
wherein the first layer structure is a chip substrate including a semiconductor substrate, and the second layer structure is the semiconductor device portion,
wherein the chip substrate including the semiconductor substrate is between the filling material and the semiconductor device portion, and
wherein the individual semiconductor chip includes the chip substrate, the semiconductor device portion and the bonding structure between the chip substrate and the semiconductor device portion.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Chu Kunmo
• Moon Changyoul
• Lee Sunghee
• Hwang Junsik

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title