Systems, methods, and apparatuses for implementing die recovery in two-level memory (2LM) stacked die subsystems

Patent metadata

Field	Value
Publication number	US-10249597-B2
Application number	US-201615283055-A
Country	US
Kind code	B2
Filing date	Sep 30, 2016
Priority date	Sep 30, 2016
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

Systems, methods, and apparatuses for implementing die recovery in Two-Level Memory (2LM) stacked die subsystems are described. A stacked semiconductor package includes a processor functional silicon die at a first layer of the stacked semiconductor package; one or more memory dies forming a corresponding one or more memory layers of the stacked semiconductor package; a plurality of Through Silicon Vias (TSV s) formed through the one or more memory dies; a plurality of physical memory interfaces electrically interfacing the one or more memory dies to the processor functional silicon die at the first layer through the memory layers via the plurality of TSVs; and a redundant physical memory interface formed by a redundant TSV traversing through the memory layers to the processor functional silicon die at the first layer through which to reroute a memory signal path from a defective physical memory interface at a defective TSV to a functional signal path traversing the redundant TSV.

First claim

What is claimed is:

1. A stacked semiconductor package, comprising:
a processor functional silicon die at a first layer of the stacked semiconductor package, wherein the processor functional silicon die comprises a TSV repair register comprising a re-routing string;
one or more memory dies forming a corresponding one or more memory layers of the stacked semiconductor package;
a plurality of Through Silicon Vias (TSVs) formed through the one or more memory dies, wherein each of the plurality of TSVs traverse through the one or more memory layers to the processor functional silicon die at the first layer of the stacked semiconductor package; a plurality of physical memory interfaces electrically interfacing the one or more memory dies to the processor functional silicon die at the first layer through the memory layers via the plurality of TSVs; and
a redundant physical memory interface formed by a redundant TSV traversing through the memory layers to the processor functional silicon die at the first layer through which to reroute a memory signal path from a defective physical memory interface at a defective TSV to a functional signal path traversing the redundant TSV.

2. The stacked semiconductor package of claim 1 :
wherein each TSV forms a physical memory path providing a continuous electrical interface from one of the memory dies through the one or more memory layers to the processor functional silicon die; and
wherein each memory signal path forms a logical memory path traversing one of the physical memory paths through the TSVs;
wherein one or more of the memory signal paths may be re-routed along the redundant physical memory interface using the redundant TSV; and
wherein a defective physical memory path associated with a defective TSV may be bypassed by re-routing the memory signal path to functional physical signal path associated with a functional TSV or the redundant physical memory interface associated with the redundant TSV.

3. The stacked semiconductor package of claim 1 :
wherein a re-routing string computed and permanently written to the stacked semiconductor package at a time of manufacture is used to reroute the memory signal path from the defective physical memory interface at the defective TSV to the functional signal path traversing the redundant TSV.

4. The stacked semiconductor package of claim 1 :
wherein the memory signal path re-routed from the defective physical memory interface to the functional signal path carries memory address and data traffic from the memory dies between one of the memory dies and the processor functional silicon die.

5. The stacked semiconductor package of claim 1 , further comprising: a package substrate layer forming a bottom layer of the stacked semiconductor package; and wherein the processor functional silicon die at the first layer of the stacked semiconductor package is affixed to the package substrate layer.

6. The stacked semiconductor package of claim 5 :
wherein a first memory die forms a first memory layer positioned atop the processor functional silicon die layer; and
wherein a second memory die forms a second memory layer positioned atop the first memory layer.

7. The stacked semiconductor package of claim 6 :
wherein the second memory die is electrically interfaced to the processor functional silicon die through the plurality of TSVs which traverse through the second first memory die at the first memory layer.

8. The stacked semiconductor package of claim 1 , wherein the stacked semiconductor package embodies a Two-Level-Memory (2LM) stacked die sub-system having one or more memory silicon dies forming the one or more memory layers and one or more functional silicon dies formed from a System On a Chip (SOC) functional silicon die having the processor functional silicon die embedded therein or a logic functional silicon die forming the processor functional silicon die or a CPU die embodying the processor functional silicon die at the first layer of the stacked semiconductor package.

9. The stacked semiconductor package of claim 1 :
wherein the first layer is formed from a System On a Chip (SOC) functional silicon die manufactured by the manufacturer of the stacked semiconductor package; and wherein a second layer is formed from a DRAM memory silicon die manufactured by a third party and acquired by the manufacturer of the stacked semiconductor package and integrated into the stacked semiconductor package by the manufacturer of the stacked semiconductor package.

10. The stacked semiconductor package of claim 1 , wherein at least one of the memory dies are formed from a phase change memory die.

11. The stacked semiconductor package of claim 1 :
wherein the processor functional silicon die comprises a System On a Chip (SOC) functional silicon die having a secured fuse block embedded therein; and
wherein a re-routing string used to reroute the memory signal path from the defective physical memory interface to the functional signal path is permanently written into the secured fuse block of the SOC functional silicon die at the time of manufacture of the stacked semiconductor package.

12. The stacked semiconductor package of claim 11 :
wherein the re-routing string is downloaded from the secured fuse block into registers of the SOC functional silicon die at every cold boot of the stacked semiconductor package.

13. A method for re-routing a memory signal path from a faulty Through Silicon Via (TSV) in a stacked semiconductor package, wherein the method comprises:
reading a re-routing string from TSV repair registers of a processor functional silicon die, wherein the processor functional silicon die forms a first layer of the stacked semiconductor package;
sending the re-routing string from the processor functional silicon die to one or more memory dies via a secure on-board connection within the stacked semiconductor package, wherein the one or more memory dies form a corresponding one or more memory layers of the stacked semiconductor package;
programming muxes at each of a plurality of TSVs formed through the one or more memory dies with the re-routing string, wherein each of the plurality of TSVs traverse through the one or more memory layers to the processor functional silicon die at the first layer of the stacked semiconductor package; and re-routing a memory signal path from a defective TSV to a redundant TSV, the redundant TSV forming a redundant physical memory interface traversing through the memory layers to the processor functional silicon die at the first layer.

14. The method of claim 13 , wherein sending the re-routing string from the processor functional silicon die to the one or more memory dies via the secure on-board connection within the stacked semiconductor package comprises sending the re-routing string over a two wire serial interface.

15. The method of claim 14 , wherein the two wire interface comprises a clock and a serial data interface from the processor functional silicon die to the one or more memory dies.

16. The method of claim 14 , wherein the two wire interface transmits the re-routing string via a serial data one bit at a time, with one bit transmitted per clock cycle.

17. The method of claim 13 , further comprising:
storing the re-routing string within a detour registers at each of the one or more memory dies; and
wherein programming the muxes at each of a plurality of TSVs with the re-routing string comprises programming the muxes at each of the plurality of TSVs at each of the one or more memory dies from the detour registers at each of the one or more memory dies

Assignees

• Intel Corp

Inventors

• Pappu Lakshminarayana
• Kolluru Kalyan C
• Vogt Pete D
• Nelson Christopher J
• Trang Amande B
• Bhattacharya Uddalak

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W72/01

  Manufacture or treatment · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00 Primary

  Package configurations · CPC title