GOA circuit

Patent metadata

Field	Value
Publication number	US-10249243-B2
Application number	US-201615506241-A
Country	US
Kind code	B2
Filing date	Dec 30, 2016
Priority date	Dec 27, 2016
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

The present invention relates to a GOA circuit. The GOA circuit of the present invention comprises a plurality of GOA circuit units which are cascade coupled, wherein n is set to be a natural number larger than 0, and the nth level GOA circuit unit comprises: a first thin film transistor (T1), a second thin film transistor (T2), a third thin film transistor (T3), a fourth thin film transistor (T4), a fifth thin film transistor (T5), a sixth thin film transistor (T6), a seventh thin film transistor (T7), an eighth thin film transistor (T8), a ninth thin film transistor (T9), a tenth thin film transistor (T10), a first capacitor (C1) and a second capacitor (C2). Moreover, two control signals (Select1, Select2) are introduced. The present invention provides a new GOA circuit. The circuit possesses MLG function, which can effectively reduce the feedthrough and improve the Vcom uniformity in the panel to promote the quality of the image display.

First claim

What is claimed is:

1. A gate driver on array (GOA) circuit, comprising a plurality of GOA circuit units which are cascade coupled, wherein n is set to be a natural number larger than 0, and the nth level GOA circuit unit comprises:
a first thin film transistor, of which a source and a drain of the first transistor are directly coupled to a first node and inputted with a forward scan control signal, and as the nth level is not one of the first two levels, a gate is coupled to a signal output point of an n−2th level GOA circuit unit, otherwise, the gate is inputted with a first activation signal;
a third thin film transistor, of which a source and a drain of the third transistor are directly coupled to the first node and inputted with a backward scan control signal, and as the nth level is not one of the last two levels, a gate is coupled to a signal output point of an n+2th level GOA circuit unit, otherwise, the gate is inputted with a second activation signal;
a seventh thin film transistor, of which a gate is coupled to the first node, and a source and a drain of the seventh transistor are directly coupled to a fourth node and a constant low voltage level;
a sixth thin film transistor, of which a gate is coupled to the fourth node, and a source and a drain of the sixth transistor are directly coupled to the first node and the constant low voltage level;
a fifth thin film transistor, of which a gate is coupled to a first constant high voltage level, and a source and a drain of the fifth transistor are directly coupled to the first node and a second node;
an eighth thin film transistor, of which a gate is inputted with a first clock signal, and a source and a drain of the eighth transistor are directly coupled to the fourth node and the first constant high voltage level;
a ninth thin film transistor, of which a gate is inputted with a first control signal, and a source and a drain of the ninth transistor are directly coupled to a third node and inputted with a second clock signal;
a tenth thin film transistor, of which a gate is inputted with a second control signal, and a source and a drain of the tenth transistor are directly coupled to the third node and a second constant high voltage level;
a second thin film transistor, of which a gate is coupled to the second node, and a source and a drain of the second transistor are directly coupled to a signal output point of the nth level GOA circuit unit and the third node;
a first capacitor, of which two ends are respectively coupled to the second node and the signal output point of the nth level GOA circuit unit;
a fourth thin film transistor, of which a gate is coupled to a fourth node, and a source and a drain of the fourth transistor are directly coupled to the signal output point of the nth level GOA circuit unit and the constant low voltage level;
a second capacitor, of which two ends are respectively coupled to the fourth node and the constant low voltage level;
at work, as the first control signal is a high voltage level, the second control signal is a low voltage level; as the first control signal is the low voltage level, the second control signal is the high voltage level.

2. The GOA circuit according to claim 1 , wherein a voltage of the second constant high voltage level is smaller than a voltage of the first constant high voltage level.

3. The GOA circuit according to claim 1 , wherein a chamfered voltage is adjusted by adjusting a voltage corresponding to the second constant high voltage level.

4. The GOA circuit according to claim 1 , wherein a chamfered duration is adjusted by adjusting a time relationship corresponding to the first control signal and the second control signal.

5. The GOA circuit according to claim 1 , wherein the first clock signal and the second clock signal are square waves that duty ratios are 0.25, and phases of the first clock signal and the second clock signal are different with a quarter cycle.

6. The GOA circuit according to claim 1 , wherein for the first two level GOA circuit units, as the forward scan starts, the gate of the first thin film transistor is inputted with a high voltage level signal to be the first activation signal.

7. The GOA circuit according to claim 1 , wherein for the last two level GOA circuit units, as the backward scan starts, the gate of the third thin film transistor is inputted with a high voltage level signal to be the second activation signal.

8. The GOA circuit according to claim 1 , wherein the circuit is a GOA circuit of a LTPS panel.

9. The GOA circuit according to claim 1 , wherein the circuit is a GOA circuit of an OLED panel.

10. A gate driver on array (GOA) circuit, comprising a plurality of GOA circuit units which are cascade coupled, wherein n is set to be a natural number larger than 0, and the nth level GOA circuit unit comprises:
a first thin film transistor, of which a source and a drain of the first transistor are directly coupled to a first node and inputted with a forward scan control signal, and as the nth level is not one of the first two levels, a gate is coupled to a signal output point of an n−2th level GOA circuit unit, otherwise, the gate is inputted with a first activation signal;
a third thin film transistor, of which a source and a drain of the third transistor are directly coupled to the first node and inputted with a backward scan control signal, and as the nth level is not one of the last two levels, a gate is coupled to a signal output point of an n+2th level GOA circuit unit, otherwise, the gate is inputted with a second activation signal;
a seventh thin film transistor, of which a gate is coupled to the first node, and a source and a drain of the seventh transistor are directly coupled to a fourth node and a constant low voltage level;
a sixth thin film transistor, of which a gate is coupled to the fourth node, and a source and a drain of the sixth transistor are directly coupled to the first node and the constant low voltage level;
a fifth thin film transistor, of which a gate is coupled to a first constant high voltage level, and a source and a drain of the fifth transistor are directly coupled to the first node and a second node;
an eighth thin film transistor, of which a gate is inputted with a first clock signal, and a source and a drain of the eighth transistor are directly coupled to the fourth node and the first constant high voltage level;
a ninth thin film transistor, of which a gate is inputted with a first control signal, and a source and a drain of the ninth transistor are directly coupled to a third node and inputted with a second clock signal;
a tenth thin film transistor, of which a gate is inputted with a second control signal, and a source and a drain of the tenth transistor are directly coupled to the third node and a second constant high voltage level;
a second thin film transistor, of which a gate is coupled to the second node, and a source and a drain of the second transistor are directly coupled to a signal output point of the nth level GOA circuit unit and the third node;
a first capacitor, of which two ends are respectively coupled to the second node and the signal output point of the nth level GOA circuit unit;
a fourth thin film transistor, of which a gate is coupled to a fourth node, and a source and a drain of the fourth transistor are directly coupled to the signal output point of the nth level GOA circuit unit and the constant low voltage level;
a second capacitor, of which two ends are respectively coupled to the fourth node and the constant low voltage level;
at work, as the first control signal is a high voltage level, the second control signal is a low voltage level; as the first control signal is the low voltage le

Assignees

• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Li Yafeng

Classifications

• G09G3/3258 Primary

  with pixel circuitry controlling the voltage across the light-emitting element · CPC title

• G09G2320/0219

  Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling · CPC title

• G09G2310/067

  Special waveforms for scanning, where no circuit details of the gate driver are given · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title