Automated attribute propagation and hierarchical consistency checking for non-standard extensions

Patent metadata

Field	Value
Publication number	US-10248749-B2
Application number	US-201815897655-A
Country	US
Kind code	B2
Filing date	Feb 15, 2018
Priority date	Aug 11, 2016
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.

First claim

What is claimed is:

1. A system for automated attribute propagation and hierarchical consistency checking, the system comprising:
a memory having computer readable instructions; and
a processing device for executing the computer readable instructions, the computer readable instructions comprising:
detecting a non-standard extension during convergence of an integrated circuit logic design;
propagating the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and
verifying a hierarchy consistency by checking the attribute propagation at each level of the plurality of hierarchies, and
wherein an integrated circuit is manufactured using the integrated circuit design.

2. The system of claim 1 , wherein detecting a non-standard extension comprises a logic designer adding a NOBUFFER attribute to a voltage sense line in the integrated circuit design.

3. The system of claim 1 , wherein propagating the non-standard extension further comprises saving the non-standard extension into a file.

4. The system of claim 1 , wherein verifying the hierarchy consistency further comprises performing a post-layout netlist checking and wherein performing the post-layout netlist checking ensures that a buffering tool did not add any additional buffers to the physical design for the integrated circuit.

5. The system of claim 4 , wherein the buffering tool comprises at least one of a buffering tool, a timing tool, and a delay tool.

6. The system of claim 1 , wherein the special constraint comprises a noise requirement.

7. The system of claim 1 , wherein the special constraint comprises a timing requirement.

8. The system of claim 1 , wherein the special constraint comprises a static voltage requirement.

9. The system of claim 1 , wherein the special constraint comprises a transient voltage requirement.

10. The system of claim 1 , wherein verifying the hierarchy consistency further comprises performing an open access checking.

11. The system of claim 1 , wherein verifying the hierarchy consistency further comprises performing a post-layout netlist checking.

12. A computer program product for automated attribute propagation and hierarchical consistency checking, the computer program product comprising:
a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processing device to cause the processing device to:
detect a non-standard extension during convergence of an integrated circuit logic design;
propagate the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and
verify a hierarchy consistency by checking the attribute propagation at each level of the plurality of hierarchies, and
wherein an integrated circuit is manufactured using the integrated circuit design.

13. The computer program product of claim 12 , wherein detecting a non-standard extension comprises a logic designer adding a NOBUFFER attribute to a voltage sense line in the integrated circuit design.

14. The computer program product of claim 12 , wherein propagating the non-standard extension further comprises saving the non-standard extension into a file.

15. The computer program product of claim 12 , wherein the special constraint comprises a noise requirement.

16. The computer program product of claim 12 , wherein the special constraint comprises a timing requirement.

17. The computer program product of claim 12 , wherein the special constraint comprises a static voltage requirement.

18. The computer program product of claim 12 , wherein the special constraint comprises a transient voltage requirement.

19. The computer program product of claim 12 , wherein verifying the hierarchy consistency further comprises performing an open access checking.

20. The computer program product of claim 12 , wherein verifying the hierarchy consistency further comprises performing a post-layout netlist checking.

Assignees

• IBM

Inventors

• Averill Iii Robert M
• Behnen Erwin
• Wolpert David S

Classifications

• G06F30/3323 Primary

  using formal methods, e.g. equivalence checking or property checking · CPC title

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F30/30

  Circuit design · CPC title

• G06F17/5036

  Physics · mapped topic

• G06F17/5045

  Physics · mapped topic