Techniques for handling interrupts in a processing unit using interrupt request queues

Patent metadata

Field	Value
Publication number	US-10248593-B2
Application number	US-201715613239-A
Country	US
Kind code	B2
Filing date	Jun 4, 2017
Priority date	Jun 4, 2017
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM) that specifies an event target number and a number of bits to ignore. In response to a slot being available in an interrupt request queue, the IPC enqueues the ENM in the slot. In response to the ENM being dequeued from the interrupt request queue, the IPC determines a group of virtual processor threads that may be potentially interrupted based on the event target number and the number of bits to ignore specified in the ENM. The event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.

First claim

What is claimed is:

1. A processing unit for a multithreaded data processing system, the processing unit comprising:
an interrupt source controller (ISC); and
an interrupt presentation controller (IPC) coupled to the ISC, wherein the IPC is configured to:
receive an event notification message (ENM), wherein the ENM specifies an event target number and a number of bits to ignore;
in response to a slot being available in an interrupt request queue of the data processing system,
enqueue the ENM in the slot; and
in response to the ENM being dequeued from the interrupt request queue, determine a group of virtual processor threads that may be potentially interrupted based on the event target number and the number of bits to ignore specified in the ENM, wherein the event target number identifies a specific virtual processor thread and the number of bits to ignore identifies a positive, integer number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.

2. The processing unit of claim 1 , wherein the IPC is further configured to:
determine whether one or more virtual processor threads within the group of virtual processor threads are dispatched and operating on an associated physical processor; and
in response to no virtual processor thread within the group of virtual processor threads being dispatched and operating on an associated physical processor, issue a reject message to a notification source specified by an event source number in the ENM.

3. The processing unit of claim 1 , wherein the IPC is further configured to:
determine whether multiple virtual processor threads within the group of virtual processor threads are dispatched and operating on an associated physical processor; and
in response to the multiple virtual processor threads within the group of virtual processor threads being dispatched and operating on an associated physical processor, select one of the multiple virtual processor threads to interrupt that does not already have a pending interrupt.

4. The processing unit of claim 3 , wherein the IPC is further configured to:
in response to more than one of the multiple virtual processor threads not already having a pending interrupt, select one of the multiple virtual processor threads to interrupt that does not already have a pending interrupt based on secondary selection criteria.

5. The processing unit of claim 4 , wherein the secondary selection criteria includes one or more of an event priority of the ENM relative to an operating priority for each of the multiple virtual processor threads, a least recently used (LRU) one of the multiple virtual processor threads, and a random one of the multiple virtual processor threads.

6. The processing unit of claim 1 , wherein the number of bits to ignore is not equal to zero and the IPC is further configured to:
determine whether multiple virtual processor threads within the group of virtual processor threads are dispatched and operating on an associated physical processor;
in response to the multiple virtual processor threads within the group of virtual processor threads being dispatched and operating on an associated physical processor, determine whether all of the multiple processor threads have pending interrupts;
in response to determining that all of the multiple processor threads have pending interrupts, determine whether an event priority of the ENM is greater than an operating priority of any of the multiple virtual processor threads; and
in response to determining that the event priority of the ENM is not greater than the operating priority of any of the multiple virtual processor threads, issue a reject message to a notification source specified by an event source number in the ENM.

7. The processing unit of claim 1 , wherein the IPC is further configured to:
in response to a slot not being available in the interrupt request queue, issue a reject message to a notification source specified by an event source number in the ENM.

8. A design structure tangibly embodied in a computer-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
an interrupt source controller (ISC); and
an interrupt presentation controller (IPC) coupled to the ISC, wherein the IPC is configured to:
receive an event notification message (ENM), wherein the ENM specifies an event target number and a number of bits to ignore;
in response to a slot being available in an interrupt request queue of a multithreaded data processing system that includes the ISC and the IPC, enqueue the ENM in the slot; and
in response to the ENM being dequeued from the interrupt request queue, determine a group of virtual processor threads that may be potentially interrupted based on the event target number and the number of bits to ignore specified in the ENM, wherein the event target number identifies a specific virtual processor thread and the number of bits to ignore identifies a positive, integer number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.

9. The design structure of claim 8 , wherein the IPC is further configured to:
in response to a slot not being available in the interrupt request queue, issue a reject message to a notification source specified by an event source number in the ENM.

Assignees

• IBM

Inventors

• Auernhammer Florian A
• Wind Daniel

Classifications

• G06F9/542

  Event management; Broadcasting; Multicasting; Notifications · CPC title

• G06F12/122

  of the least frequently used [LFU] type, e.g. with individual count value · CPC title

• G06F2212/70

  Details relating to dynamic memory management · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F12/12

  Replacement control · CPC title