Cache coherency for direct memory access operations

Patent metadata

Field	Value
Publication number	US-10248567-B2
Application number	US-201415319693-A
Country	US
Kind code	B2
Filing date	Jun 16, 2014
Priority date	Jun 16, 2014
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

Methods, apparatus, systems and articles of manufacture are disclosed to maintain cache coherency. Examples disclosed herein involve, in response to receiving, from a direct memory access controller, an interrupt associated with a direct memory access operation, handling the interrupt based on a parameter of the direct memory access operation, wherein the direct memory access controller is to execute the direct memory access operation.

First claim

What is claimed is:

1. A non-transitory computer readable storage medium comprising instructions that, when executed, cause a processor to at least:
receive, from a direct memory access controller, an interrupt associated with a direct memory access operation; and
handle the interrupt via the processor to maintain cache coherency based on a direction of the direct memory access operation, the interrupt generated by the direct memory access controller and comprising the direction, wherein the direction of the direct memory access operation includes:
a direct memory access operation from a memory to a peripheral; or
a direct memory access operation from the peripheral to the memory;

wherein the direct memory access controller is to execute the direct memory access operation.

2. The non-transitory computer readable storage medium of claim 1 , wherein the instructions, when executed cause the processor to:
handle the interrupt by flushing a cache associated with the direct memory access operation in response to the direction of the direct memory access operation being from the memory to the peripheral.

3. The non-transitory computer readable storage medium of claim 1 , wherein the instructions, when executed cause the processor to:
handle the interrupt by invalidating a location of a cache corresponding to a memory location of the direct memory access operation in response to the direction of the direct memory access operation being from the peripheral to the memory.

4. The non-transitory computer readable storage medium of claim 1 , wherein firmware of the processor comprises the instructions.

5. The non-transitory computer readable storage medium of claim 1 , the instructions comprise a first software layer of a processor and the direct memory access operation was initiated by a module running on a second software layer of the processor.

6. A system comprising:
a direct memory access controller to:
determine that a direct memory access operation is to be executed;
generate an interrupt indicating that the direct memory access operation is to be executed, wherein the interrupt includes a direction of the direct memory access operation, the direction of the direct memory access operation including:
a direct memory access operation from a memory of the system to a peripheral communicatively coupled with the system; or
a direct memory access operation from the peripheral communicatively coupled with the system to the memory of the system;

send the interrupt to a cache coherency manager of a processor; and

the processor comprising the cache coherency manager to handle the interrupt based on the direction of the direct memory access operation.

7. The system of claim 6 , wherein the cache coherency manager is to handle the interrupt by flushing a cache of the system in response to the direction of the direct memory access operation being from the memory of the system to the peripheral communicatively coupled with the system.

8. The system of claim 6 , wherein the cache coherency manager is to handle the interrupt by invalidating a location of a cache corresponding to a memory location of the direct memory access operation in response to the direction of the direct memory access operation being from the peripheral of the system to the memory of the system.

9. The system of claim 6 , wherein the cache coherency manager is a portion of system firmware, the system firmware comprising computer readable instructions to run a processor platform of the system.

10. A method comprising:
determining, via a hardware direct memory access controller, that a direct memory access operation is to be executed;
generating, via the hardware direct memory access controller, an interrupt corresponding to the direct memory access operation, wherein the interrupt includes a direction of the direct memory access operation, the direction of the direct memory access operation including:
a direct memory access operation from a memory associated with the direct memory access operation to a peripheral; or
a direct memory access operation from the peripheral to the memory associated with the direct memory access operation;

sending, via the hardware direct memory access controller, the interrupt to a cache coherency manager of a processor, the cache coherency manager to handle the interrupt based on the direction of the direct memory access operation to maintain cache coherency.

11. The method of claim 10 , wherein determining that the direct memory access operation is to be executed comprises receiving a data request from a first software layer of a processor.

12. The method of claim 11 , wherein a second software layer of the processor comprises the cache coherency manager, the first software layer being different from the second software layer.

13. The method of claim 10 , wherein the interrupt indicates that the cache coherency manager is to flush a cache associated with the memory associated with the direct memory access operation in response to the direction of the direct memory access operation being from the memory to the peripheral.

14. The method of claim 10 , wherein the interrupt indicates that the cache coherency manager is to invalidate a cache location corresponding a location of the memory associated with the direct memory access operation when the direction of the direct memory access operation is from the peripheral to the memory associated with the direct memory access operation.

Assignees

• Hewlett Packard Development Co

Inventors

• Ramakrishnan Senthil Kumar
• Cohen Eugene

Classifications

• G06F2212/1008

  Correctness of operation, e.g. memory ordering · CPC title

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06F12/0815

  Cache consistency protocols · CPC title

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title