Run time ECC error injection scheme for hardware validation

Patent metadata

Field	Value
Publication number	US-10248521-B2
Application number	US-201615089352-A
Country	US
Kind code	B2
Filing date	Apr 1, 2016
Priority date	Apr 2, 2015
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

Systems and methods for a run-time error correction code (“ECC”) error injection scheme for hardware validation are disclosed. The systems and methods include configuring a read path to internally forward read data, and injecting at least one faulty bit into the forwarded read data via a read fault injection logic. The systems and methods may also include configuring a write path to internally forward write data, and injecting at least one faulty bit into the forwarded write data via a write fault injection logic.

First claim

What is claimed is:

1. An integrated peripheral device having a runtime self-test capabilities, comprising
a read path configured to internally forward read data;
a read fault injection logic configured to, under program control, inject at least one faulty bit into the forwarded read data; and
an error indication logic configured to, under program control, provide an error indication to a processor when a fault injection occurs;
wherein the read fault injection logic is further configured to inject the at least one faulty bit into the forwarded read data when a user has enabled the injection and when a read address matches a user-specified memory location.

2. The integrated peripheral device of claim 1 , further comprising
a write path configured to internally forward write data;
a write fault injection logic configured to, under program control, inject at least one faulty bit into the forwarded write data; and
an error indication logic configured to, under program control, provide an error indication to a processor when a location associated with the fault injection is accessed.

3. The integrated peripheral device of claim 1 , wherein the peripheral device is an Error Correction Code module in a microcontroller.

4. The integrated peripheral device of claim 1 , wherein the read path has a width of 136 bits.

5. The integrated peripheral device of claim 1 , wherein the at least one faulty bit comprises a faulty parity bit.

6. The integrated peripheral device of claim 2 , wherein the at least one faulty bit comprises a faulty parity bit.

7. The integrated peripheral device of claim 2 , wherein the write fault injection logic is further configured to inject the at least one faulty bit into the forwarded write data when the user has enabled the injection and when the write address matches a user-specified memory location.

8. The integrated peripheral device of claim 1 , further comprising error detection logic configured to, under program control, notify an ECC system that an error is present based at least on the at least one faulty bit in the forwarded read data.

9. The integrated peripheral device of claim 2 , further comprising error detection logic configured to, under program control, notify an ECC system that an error is present based at least on the at least one faulty bit in the forwarded write data.

10. An integrated peripheral device having a runtime self-test capabilities, comprising
a write path configured to internally forward write data;
a write fault injection logic configured to, under program control, inject at least one faulty bit into the forwarded write data when a user has enabled the injection and when a write address matches a user-specified memory location.

11. The integrated peripheral device of claim 10 , wherein the peripheral device is an Error Correction Code module in a microcontroller.

12. The integrated peripheral device of claim 10 , wherein the read path has a width of 136 bits.

13. The integrated peripheral device of claim 10 , wherein the at least one faulty bit comprises a faulty parity bit.

14. The integrated peripheral device of claim 10 , further comprising error detection logic configured to, under program control, notify an ECC system that an error is present based at least on the at least one faulty bit in the forwarded write data.

15. A method for implementing a run-time ECC error injection scheme for hardware validation, the method comprising:
configuring a read path to internally forward read data; and
injecting at least one faulty bit into the forwarded read data via a read fault injection logic when a user has enabled the injection and when a read address matches a user-specified memory location.

16. The method of claim 15 , further comprising
configuring a write path to internally forward write data; and
injecting at least one faulty bit into the forwarded write data via a write fault injection logic.

17. The method of claim 15 , wherein the peripheral device is an Error Correction Code module in a microcontroller.

18. The method of claim 15 , wherein the at least one faulty bit comprises a faulty parity bit.

Assignees

• Microchip Tech Inc

Inventors

• Catherwood Michael
• Ivey Brant
• Rangarajan Sankar

Classifications

• G06F11/2215 Primary

  to test error correction or detection circuits · CPC title

• G06F11/10 Primary

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title

• G06F11/2205

  using arrangements specific to the hardware being tested · CPC title

• G06F11/263 Primary

  Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers} · CPC title