Data processing device

Patent metadata

Field	Value
Publication number	US-10248156-B2
Application number	US-201515502771-A
Country	US
Kind code	B2
Filing date	Mar 20, 2015
Priority date	Mar 20, 2015
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

In a data processing device including two sets of circuit pairs which are respectively duplicated in two clock domains which are asynchronous to each other, an asynchronous transfer circuit that transfers a payload signal is provided between the two sets of circuit pairs. The asynchronous transfer circuit includes two sets of a pair of bridge circuits which are respectively connected to the two sets of circuit pairs, and asynchronously transfers the payload signal and a control signal indicating a timing at which the payload signal is stable on a reception side. The two sets of a pair of bridge circuits and the payload signals can be duplicated, but the control signal is not duplicated, and the received payload signal is used for timing control to supply an expected same time difference, to the pair of duplicated circuits. This enables asynchronous transfer between circuits duplicated in the asynchronous clock domains.

First claim

What is claimed is:

1. A data processing device comprising:
a first body circuit and a first check circuit which are duplicated to each other in a first clock domain;
a second body circuit and a second check circuit which are duplicated to each other in a second clock domain which is asynchronous to the first clock domain; and
an asynchronous transfer circuit that transfers a payload signal between the first clock domain and the second clock domain,
wherein the asynchronous transfer circuit
includes a first body-side bridge circuit and a first check-side bridge circuit which are respectively connected to the first body circuit and the first check circuit and are duplicated to each other in the first clock domain, and a second body-side bridge circuit and a second check-side bridge circuit which are respectively connected to the second body circuit and the second check circuit and are duplicated to each other in the second clock domain, and
has control signals which are generated by first or second body-side bridge circuit which transmits the payload signal and indicate a timing at which the payload signal is stable on a reception side, compares the control signal and check control signal which are generated by the corresponding first or second check-side bridge circuit, and in a case of mismatch, detects as a failure.

2. The data processing device according to claim 1 ,
wherein the first body circuit and the first check circuit respectively perform the same data processing with a time difference of a first number of cycles of 0 or more cycles in the first clock domain,
wherein the second body circuit and the second check circuit respectively perform the same data processing with a time difference of a second number of cycles of 0 or more cycles in the second clock domain,
wherein the asynchronous transfer circuit compares an output from the first body circuit and an output from the first check circuit with a time difference of the first number of cycles in the first clock domain, and in a case of mismatch, detects as a failure, and
wherein the comparison between the control signal and the corresponding check control signal is performed with a time difference of the first number of cycles in the first clock domain, and the comparison is performed with a time difference of the second number of cycles in the second clock domain.

3. The data processing device according to claim 1 ,
wherein the first body-side bridge circuit transfers the payload signal and the control signals to the second body-side bridge circuit,
wherein the first check-side bridge circuit generates a check payload signal and the check control signals, and transfers the check payload signal to the second check-side bridge circuit,
wherein the asynchronous transfer circuit compares the control signal and the check control signal in the first clock domain, and in a case of mismatch, detects as a failure,
wherein the asynchronous transfer circuit transfers the control signal to the second clock domain, and
wherein based on the control signal which is transferred to the second clock domain, the second body-side bridge circuit receives the payload signal, the second check-side bridge circuit receives the check payload signal, and the asynchronous transfer circuit compares the payload signal and the check payload signal which are respectively received by the second body-side bridge circuit and the second check-side bridge circuit, and in a case of mismatch, detects as a failure.

4. The data processing device according to claim 3 ,
wherein the first body circuit and the first check circuit respectively perform the same data processing with a time difference of a first number of cycles of 0 or more cycles in the first clock domain,
wherein the second body circuit and the second check circuit respectively perform the same data processing with a time difference of a second number of cycles of 0 or more cycles in the second clock domain,
wherein the asynchronous transfer circuit compares an output from the first body circuit and an output from the first check circuit with a time difference of the first number of cycles in the first clock domain, and in a case of mismatch, detects as a failure,
wherein the comparison between the control signal and the corresponding check control signal is performed with a time difference of the first number of cycles in the first clock domain, and
wherein the comparison between the payload signal and the check payload signal is performed with a time difference of the second number of cycles in the second clock domain.

5. The data processing device according to claim 1 ,
wherein the first body-side bridge circuit transfers the payload signal and the control signals to the second body-side bridge circuit,
wherein the first check-side bridge circuit generates the check payload signal and the check control signal, and transfers the check payload signal and the check control signal to the second check-side bridge circuit,
wherein the asynchronous transfer circuit compares the control signal and the check control signal in the second clock domain while allowing shift up to one cycle, and in a case of mismatch, detects as a failure, and
wherein based on the control signal which is transferred to the second clock domain, the second body-side bridge circuit receives the payload signal, the second check-side bridge circuit receives the check payload signal, and the asynchronous transfer circuit compares the payload signal and the check payload signal which are respectively received by the second body-side bridge circuit and the second check-side bridge circuit, and in a case of mismatch, detects as a failure.

6. The data processing device according to claim 5 ,
wherein the first body circuit and the first check circuit respectively perform the same data processing with a time difference of a first number of cycles of 0 or more cycles in the first clock domain,
wherein the second body circuit and the second check circuit respectively perform the same data processing with a time difference of a second number of cycles of 0 or more cycles in the second clock domain,
wherein the asynchronous transfer circuit compares the output from the first body circuit and the output from the first check circuit with a time difference of the first number of cycles in the first clock domain, and in a case of mismatch, detects as a failure,
wherein the comparison between the control signal and the corresponding check control signal is performed in the second clock domain with a time difference obtained by adding a margin of plus or minus one cycle to the second number of cycles, if the signals match within the time difference including the margin, it is determined to match, and in a case of mismatch within a range of the margin, it is detected as a failure, and
wherein the comparison between the payload signal and the check payload signal is performed with a time difference of the second number of cycles in the second clock domain.

7. The data processing device according to claim 5 ,
wherein the second body-side bridge circuit includes a second body-side flip-flop that receives the payload signal,
wherein the second check-side bridge circuit includes a second check-side flip-flop that receives the check payload signal, and
wherein the asynchronous transfer circuit compares three signals which are a signal for providing an acquisition timing of the payload signal to the second body-side flip-flop based on the control signal, a signal for providing an acquisition timing of the check payload signal to the second check-side flip-flop based on the control signal, and the check control signal, and in a case where at least one signal does not match the other signals, detects as a failure.

Assignees

• Renesas Electronics Corp

Inventors

• Yuyama Yoichi
• Takada Kiwamu

Classifications

• G06F13/4213

  with asynchronous protocol · CPC title

• G06F11/1675

  Temporal synchronisation or re-synchronisation of redundant processing components · CPC title

• H04L12/5601

  Transfer mode dependent, e.g. ATM · CPC title

• H04L2012/566

  using the ATM layer · CPC title

• G06F11/1641

  where the comparison is not performed by the redundant processing components · CPC title