Bias circuit

Patent metadata

Field	Value
Publication number	US-10248149-B2
Application number	US-201715839189-A
Country	US
Kind code	B2
Filing date	Dec 12, 2017
Priority date	Mar 24, 2017
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

A bias circuit includes a first transistor, a second transistor, a first resistor and a second resistor. The first end of the first transistor is coupled to a first voltage source. One end of the first resistor is coupled to the second end of the first transistor, and the other end of the first resistor is coupled to the control terminal of the first transistor. The first end of the second transistor is coupled to a second voltage source, and the second end of the second transistor is coupled to the control terminal of the first transistor. One end of the second resistor is coupled to the other end of the first resistor, and the other end of the second resistor is coupled to the control terminal of the second transistor.

First claim

What is claimed is:

1. A bias circuit, comprising:
a first transistor, wherein a first end of the first transistor is coupled to a first voltage source;
a first resistor, having one end coupled to a second end of the first transistor, having the other end coupled to a control terminal of the first transistor;
a second transistor, wherein a first end of the second transistor is coupled to a second voltage source, and a second end of the second transistor is coupled to the control terminal of the first transistor; and
a second resistor, having one end coupled to the other end of the first resistor, having the other end coupled to a control terminal of the second transistor,
wherein a reference voltage is generated at a first node between the second end of the first transistor and the one end of the first resistor, and the reference voltage is related to a sum of a voltage drop between the control terminal and the second end of the first transistor and a voltage drop between the control terminal and the second end of the second transistor.

2. The bias circuit according to claim 1 , wherein when the first transistor is turned on by the first voltage source and the second transistor is turned on by the second voltage source, a first current flows through the first transistor and a second current flows through the second transistor, the reference voltage is generated when the first current flows through the first resistor and the first current and the second current flow through the second resistor, and a bias current is generated at a second node between the control terminal of the second transistor and the other end of the second resistor.

3. The bias circuit according to claim 2 , wherein after the first transistor is turned on by the first voltage source and the second transistor is turned on by the second voltage source, when the voltage of the first voltage source or the voltage of the second voltage source varies, the current values of the first current, the second current and the bias current are maintained.

4. The bias circuit according to claim 2 , wherein the reference voltage is provided to a load circuit.

5. The bias circuit according to claim 2 , wherein when the first transistor is turned on by the first voltage source and the second transistor is turned on by the second voltage source, the voltage at the second end of the first transistor and the voltage at the second end of the second transistor are larger than the voltage at the control terminal of the first transistor and larger than the voltage at the control terminal of the second transistor.

6. The bias circuit according to claim 5 , wherein the first transistor and the second transistor are depletion mode transistors, the first end of the first transistor and the first end of the second transistor are drains, the second end of the first transistor and the second end of the second transistor are sources, and the control terminal of the first transistor and the control terminal of the second transistor are gates.

7. The bias circuit according to claim 2 , wherein the voltage of the first voltage source and the voltage of the second voltage source are equal or unequal to each other.

8. The bias circuit according to claim 2 , wherein the reference voltage is provided to a first load circuit at the first node, and the bias current is outputted to a second load circuit from the second node.

9. The bias circuit according to claim 1 , wherein the reference voltage is provided to a load circuit at the first node.

10. The bias circuit according to claim 1 , further comprising:
a third transistor, wherein a first end of the third transistor is coupled to a third voltage source, and a second end of the third transistor is coupled to the control terminal of the second transistor; and
a third resistor, having one end coupled to the other end of the second resistor, having the other end coupled to a control terminal of the third transistor;
wherein when the first transistor is turned on by the first voltage source, the second transistor is turned on by the second voltage source and the third transistor is turned on by the third voltage source, a first current flows through the first transistor, a second current flows through the second transistor and a third current flows through the third transistor, the reference voltage is generated when the first current flows through the first resistor, the first current and the second current flow through the second resistor, and the first current, the second current and the third current flow through the third resistor, and a bias current is generated at a third node between the control terminal of the third transistor and the other end of the third resistor.

11. The bias circuit according to claim 10 , wherein after the first transistor is turned on by the first voltage source, the second transistor is turned on by the second voltage source and the third transistor is turned on by the third voltage source, when the voltage of the first voltage source, the voltage of the second voltage source or the voltage of the third voltage source varies, the current values of the first current, the second current, the third current and the bias current are maintained.

12. The bias circuit according to claim 10 , wherein the reference voltage is further related to a sum of the voltage drop between the control terminal and the second end of the first transistor, the voltage drop between the control terminal and the second end of the second transistor, and a voltage drop between the control terminal and the second end of the third transistor.

13. The bias circuit according to claim 10 , wherein when the first transistor is turned on by the first voltage source, the second transistor is turned on by the second voltage source and the third transistor is turned on by the third voltage source, the voltage at the second end of the first transistor, the voltage at the second end of the second transistor and the voltage at the second end of the third transistor are larger than the voltage at the control terminal of the first transistor, larger than the voltage at the control terminal of the second transistor, and larger than the voltage at the control terminal of the third transistor.

14. The bias circuit according to claim 13 , wherein the first transistor, the second transistor and the third transistor are depletion mode transistors, the first end of the first transistor, the first end of the second transistor and the first end of the third transistor are drains, the second end of the first transistor, the second end of the second transistor and the second end of the third transistor are sources, and the control terminal of the first transistor, the control terminal of the second transistor and the control terminal of the third transistor are gates.

15. The bias circuit according to claim 10 , wherein the voltages of any two of the first voltage source, the second voltage source and the third voltage source are equal or unequal to each other.

16. The bias circuit according to claim 10 , wherein the bias current is outputted to a load circuit from the third node.

17. The bias circuit according to claim 10 , wherein the reference voltage is provided to a load circuit at the first node, the bias current is outputted to the load circuit from the third node, and the load circuit has an input end and an output end and includes:
a fourth transistor, wherein the first end of the fourth transistor receives the bias current, the second end of the fourth transistor is coupled to a reference potential, and the control termina

Assignees

• Richwave Technology Corp

Inventors

• Chen Chih-Sheng
• Peng Tien-Yun
• Lin Jhao-Yi

Classifications

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F2200/294

  the amplifier being a low noise amplifier [LNA] · CPC title

• H03F1/301

  in MOSFET amplifiers (H03F1/303, H03F1/305, H03F1/308 take precedence) · CPC title

• H03F1/223

  with MOSFET's · CPC title

• G05F1/561 Primary

  Voltage to current converters (amplifiers H03F) · CPC title