High resolution temperature sensor

Patent metadata

Field	Value
Publication number	US-10247621-B1
Application number	US-201615264583-A
Country	US
Kind code	B1
Filing date	Sep 13, 2016
Priority date	Sep 13, 2015
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

In a high resolution temperature sensor, first and second MEMS resonators generate respective first and second clock signals and a locked-loop reference clock generator generates a reference clock signal having a frequency that is phase-locked to at least one of the first and second clock signals. A frequency-ratio engine within the MEMS temperature sensor oversamples at least one of the first and second clock signals with the reference clock signal to generate a ratio of the frequencies of the first and second clock signals.

First claim

What is claimed is:

1. A microelectromechanical-system (MEMS) temperature sensor comprising:
first and second MEMS resonators to generate respective first and second clock signals;
a locked-loop reference clock generator to generate a reference clock signal having a frequency that is phase-locked to at least one of the first and second clock signals; and
a frequency-ratio engine that oversamples at least one of the first and second clock signals using the reference clock signal to generate, as an indication of temperature, a ratio of the frequencies of the first and second clock signals;
wherein the locked-loop reference clock generator phase-locks the reference clock signal to the first clock signal and wherein the frequency-ratio engine comprises a phase quantizer that generates a stream of quantization values indicative of (i) a frequency ratio between the second clock signal and the reference clock signal and (ii), by virtue of the phase-lock between the reference clock signal and the first clock signal, a frequency ratio between the second clock signal and the first clock signal.

2. The MEMS temperature sensor of claim 1 wherein the first and second MEMS resonators are co-located within a single integrated circuit die.

3. The MEMS temperature sensor of claim 1 wherein the locked-loop reference clock generator to generate the reference clock signal comprises circuitry to effect oscillation of the reference clock signal at a frequency substantially higher than the frequencies of the first and second clock signals.

4. The MEMS temperature sensor of claim 1 wherein the locked-loop reference clock generator to generate the reference clock signal comprises circuitry to effect oscillation of the reference clock signal at a frequency that is an integer multiple of the frequency of at least one of the first and second clock signals.

5. The MEMS temperature sensor of claim 1 wherein the frequency-ratio engine implements a phase-locked loop in which the locked-loop reference clock generator constitutes a digitally controlled oscillator.

6. A microelectromechanical-system (MEMS) temperature sensor comprising:
first and second MEMS resonators to generate respective first and second clock signals;
a locked-loop reference clock generator to generate a reference clock signal having a frequency that is phase-locked to at least one of the first and second clock signals; and
a frequency-ratio engine that oversamples at least one of the first and second clock signals using the reference clock signal to generate, as an indication of temperature, a ratio of the frequencies of the first and second clock signals, wherein the frequency-ratio engine comprises a digital phase locked-loop and wherein the locked-loop reference clock generator comprises a phased locked loop nested within and controlled by the digital phase-locked loop.

7. The MEMS temperature sensor of claim 1 wherein the locked-loop reference clock generator comprises a fractional-N phase locked loop.

8. The MEMS temperature sensor of claim 1 wherein the locked-loop reference clock generator comprises a ring oscillator having a plurality of inverter stages and wherein the phase quantizer comprises a fine quantizer circuit to generate the stream of quantization values with a resolution according to a time interval between state transitions within individual pairs of inverter stages within the plurality of inverter stages.

9. The MEMS temperature sensor of claim 1 wherein the locked-loop reference clock generator comprises a ring oscillator having a plurality (N) of inverter stages and wherein the phase quantizer quantizes one or more cycles of the second clock signal with a temporal resolution of 1/N th the reference clock period or less.

10. A method of operation within a microelectromechanical-system (MEMS) temperature sensor, the method comprising:
generating first and second clock signals based on oscillatory signals from first and second MEMS resonators, respectively;
generating a reference clock signal having a frequency that is phase-locked to at least one of the first and second clock signals; and
oversampling at least one of the first and second clock signals using the reference clock signal to generate, as an indication of temperature, a ratio of the frequencies of the first and second clock signals;
wherein generating the reference clock signal comprises phase-locking the reference clock signal to the first clock signal and wherein oversampling at least one of the first and second clock signals comprises generating a stream of quantization values indicative of (i) a frequency ratio between the second clock signal and the reference clock signal and (ii), by virtue of the phase-lock between the reference clock signal and the first clock signal, a frequency ratio between the second clock signal and the first clock signal.

11. The method of claim 10 wherein the first and second MEMS resonators are co-located within a single integrated circuit die.

12. The method of claim 10 wherein generating the reference clock signal comprises generating a reference clock signal having a frequency substantially higher than the frequencies of the first and second clock signals.

13. The method of claim 10 wherein generating the reference clock signal comprises generating the reference clock signal at a frequency that is an integer multiple of the frequency of at least one of the first and second clock signals.

14. The method of claim 10 wherein oversampling at least one of the first and second clock signals using the reference clock signal comprises generating a digital feedback signal that controls the frequency of the reference clock signal within a phase-locked loop.

15. The method of claim 10 wherein generating the reference clock signal comprises generating the reference clock signal within a fractional-N phase locked loop.

16. The method of claim 10 wherein generating the stream of quantization values comprises generating the stream of quantization values with a resolution according to a time interval between state transitions within individual pairs of inverter stages within a ring oscillator.

17. The method of claim 10 wherein generating the reference clock signal comprises generating the reference clock signal within a ring oscillator having a plurality (N) of inverter stages and wherein generating the stream of quantization values comprises quantizing one or more cycles of the second clock signal with a temporal resolution of 1/N th the reference clock period or less.

18. A method of operation within a microelectromechanical-system (MEMS) temperature sensor, the method comprising:
generating first and second clock signals based on oscillatory signals from first and second MEMS resonators, respectively;
generating a reference clock signal having a frequency that is phase-locked to at least one of the first and second clock signals; and
oversampling at least one of the first and second clock signals using the reference clock signal to generate, as an indication of temperature, a ratio of the frequencies of the first and second clock signals;
wherein generating the reference clock signal comprises generating the reference clock signal within a first phase locked loop and wherein oversampling at least one of the first and second clock signals using the reference clock signal comprises oversampling at least one of the first and second clock signals within a second phase locked loop, wherein the first phase locked loop is digitally controlled by a feedback signal generated within the second phase locked

Assignees

• Sitime Corp

Inventors

• Partridge Aaron
• Zaliasl Samira
• Roshan Meisam Heidarpour
• Tabatabaei Sassan

Classifications

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L7/0991

  the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814) · CPC title

• H03K3/0315 Primary

  Ring oscillators · CPC title

• H03L7/1976

  using a phase accumulator for controlling the counter or frequency divider · CPC title

• H03L1/027

  by using frequency conversion means which is variable with temperature, e.g. mixer, frequency divider, pulse add/subtract logic circuit (H03L1/023, H03L1/026 take precedence) · CPC title