Substrate with insulating layer

US10244647B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10244647-B2
Application numberUS-201415031594-A
CountryUS
Kind codeB2
Filing dateFeb 14, 2014
Priority dateFeb 14, 2014
Publication dateMar 26, 2019
Grant dateMar 26, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A substrate with a Micro-Arc Oxidation (MAO) layer or an electrophoretic deposition (ED) layer on a first side of the substrate and an electrically insulating layer on a second side of the substrate.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of treating a substrate comprising a first surface and a second surface, the first surface and the second surface being electrically conductive surfaces on opposite sides of the substrate, the method comprising: applying an electrically insulating coating to the first surface of the substrate before performing a Micro-Arc Oxidation (MAO) or an electrophoretic deposition (ED); immersing the substrate with the electrically insulating coating on the first surface into a bath of an electrolyte solution; and performing the MAO or the ED on the second surface of the substrate, wherein the electrically insulating coating covers at least 80% of the first surface of the substrate, wherein the first surface is an inside surface of a casing for an electronic device and the second surface is an outside surface of the casing. 2. The method of claim 1 , wherein the electrically insulating coating is applied by spray coating, film transfer, physical vapor deposition, or printing. 3. The method of claim 1 , wherein the electrically insulating coating covers the entire first surface of the substrate so that after performing the MAO or the ED, the first surface is not covered with an MAO or ED layer. 4. The method of claim 1 , wherein the substrate has an edge connecting the first surface and the second surface and wherein the insulating coating is applied to said edge as well as to the first surface of the substrate. 5. The method of claim 1 , wherein after the performing the MAO or the ED, at least 90% of the second surface is covered with a MAO layer or an ED layer. 6. The method of claim 1 , wherein the electrically insulating layer comprises a material selected from the group comprising: polyimides, ABS (Acrylonitrile, butadiene and styrene), polyacetate, polyacrylics, nylon, epoxy, fluoropolymer, Neoprene, PEEK (PolyEtherEther-Ketone), PET (Polyethylene terephthalate), phenolics, polycarbonate, polyester, polyolefins, polystyrene, polysulfones, polyurethanes, polyvinylchloride (PVC), silicone rubber, PEI (polyetherimide), and low dielectric constant materials. 7. The method of claim 1 , wherein the MAO is carried out with an electrolyte including a material selected from the group comprising: silicate, aluminate, sulfate, aluminum powder, aluminum alloy powder, zinc oxide, sodium hydroxide, potassium hydroxide, potassium fluoride, aluminum hydroxide, borate, carbonate, rare earth element, and aluminum oxide (Al 2 O 3 ). 8. The method of claim 1 , wherein the electrophoretic deposition comprises a polymer in combination with particles selected from the group comprising inorganic particles and metallic particles. 9. A casing for an electronic device comprising: a substrate, a Micro-Arc Oxidation (MAO) layer or an electrophoretic deposition (ED) layer on an exterior surface of the substrate; and an electrically insulating layer on an inner surface of the substrate to prevent the MAO layer or the ED layer from forming on portions of the substrate with the electrically insulating layer when the substrate is immersed in a bath of an electrolyte solution, wherein the exterior surface of the substrate faces an exterior of the casing and the inner surface of the substrate faces an interior of the casing. 10. The casing of claim 9 , wherein the insulating layer comprises a material selected from the group comprising: polyimides, ABS (Acrylonitrile, butadiene and styrene), polyacetates, polyacrylics, nylon, epoxy, fluoropolymers, Neoprene, PEEK (PolyEtherEther-Ketone), PET (Polyethylene terephthalate), phenolics, polycarbonates, polyesters, polyolefins, polystyrene, polysulfones, polyurethane, polyvinylchloride (PVC), silicone rubber, PEI (polyetherimide), and low dielectric constant materials. 11. The casing of claim 9 , wherein the MAO layer comprises a metal oxide which has an at least partially crystalline structure. 12. The casing of claim 9 , wherein the substrate comprises a plurality of electrically conductive layers between the ED or MAO layer and the electrically insulating layer. 13. A casing for an electronic device comprising: a substrate having a surface area; a first portion of the surface area of the substrate being covered with an electrically insulating layer; and a second portion of the surface area of the electrically conductive substrate being covered with a Micro-Arc Oxidation (MAO) layer or an electrophoretic deposition (ED) layer, wherein the electrically insulating layer is to prevent the MAO layer or the ED layer from forming on the first portion of the surface area of the substrate that is covered with the electrically insulating layer when the substrate is immersed in a bath of an electrolyte solution, wherein the first portion comprises at least 45% of the surface area of the substrate, wherein the first portion of the surface area includes an inside surface of the casing and the second portion of the surface area includes an outside surface of the casing. 14. The casing of claim 13 , wherein the substrate comprises a light metal or light metal alloy selected from the group comprising aluminum, magnesium, lithium, titanium, zinc, and their alloys.

Assignees

Inventors

Classifications

  • H05K5/0247Primary

    Electrical details of casings, e.g. terminals, passages for cables or wiring · CPC title

  • Servicing or operating {apparatus or multistep processes} · CPC title

  • Tubes; Rings; Hollow bodies · CPC title

  • of metals or alloys not provided for in groups C25D11/04 - C25D11/32 · CPC title

  • Anodisation with spark discharge · CPC title

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What does patent US10244647B2 cover?
A substrate with a Micro-Arc Oxidation (MAO) layer or an electrophoretic deposition (ED) layer on a first side of the substrate and an electrically insulating layer on a second side of the substrate.
Who is the assignee on this patent?
Hewlett Packard Development Co
What technology area does this patent fall under?
Primary CPC classification H05K5/0247. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 26 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).