Interfacing between SFQ and NRZ data encodings

Patent metadata

Field	Value
Publication number	US-10243582-B1
Application number	US-201815937418-A
Country	US
Kind code	B1
Filing date	Mar 27, 2018
Priority date	Mar 27, 2018
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

Superconducting interface circuits and methods convert between non-return-to-zero (NRZ) encoded voltage signals and reciprocal quantum logic (RQL) compliant signals of opposite-polarity single flux quantum (SFQ) pulse pairs, and vice-versa, so as to provide high-speed NRZ input to, and output from, RQL computing circuitry.

First claim

What is claimed is:

1. Superconducting interface circuitry for converting non-return-to-zero (NRZ) encoded voltage signals to reciprocal quantum logic (RQL) compliant signals of opposite-polarity single flux quantum (SFQ) pulse pairs, the circuitry comprising:
an input Josephson transmission line (JTL) configured to convert an input voltage level of one of two binary states to an SFQ pulse;
a reflecting JTL, connected to the input JTL, configured to reflect and invert the SFQ pulse as an inverted SFQ pulse; and
an output JTL, connected to the input JTL and the reflecting JTL, configured to transmit as an RQL-encoded output signal the SFQ pulse and, subsequently, the inverted SFQ pulse, as an opposite-polarity SFQ pulse pair.

2. The interface circuitry of claim 1 , wherein the circuitry is configured to reflect the inverted SFQ pulse into the input JTL to reset the input JTL.

3. The interface circuitry of claim 1 , wherein the circuitry is configured to transmit the inverted SFQ pulse from the output JTL within the same clock cycle as the SFQ pulse.

4. The interface circuitry of claim 3 , wherein the circuitry is configured to transmit the inverted SFQ pulse from the output JTL one half clock cycle later than the SFQ pulse.

5. The interface circuitry of claim 1 , wherein the reflecting JTL is connected to ground via an inductor.

6. The interface circuitry of claim 1 , wherein the circuitry is configured to successively transmit opposite-polarity pulse pairs, one pair per clock cycle, as long as the input voltage level remains the one of two binary states.

7. The interface circuitry of claim 1 , wherein the reflecting JTL comprises exactly two Josephson junctions each sized to have a critical current of about 35 microamps.

8. The interface circuitry of claim 1 , wherein at least one of the input JTL and the output JTL comprises exactly two Josephson junctions, one of the Josephson junctions being sized to have a critical current of about 35 microamps and the other of the Josephson junctions being sized to have a critical current of about 50 microamps.

9. The interface circuitry of claim 1 , wherein each of the three JTLs is biased by an RQL clock signal.

10. A superconducting computing system comprising:
the interface circuitry of claim 1 ;
RQL circuitry configured to perform computation using, at least in part, the RQL-compliant signals, to produce RQL-compliant result signals comprising opposite-polarity SFQ pulse pairs; and
output superconducting circuitry configured to convert the RQL-compliant result signals to NRZ-encoded output voltage signals.

11. Superconducting interface circuitry for converting reciprocal quantum logic (RQL) compliant signals of opposite-polarity single flux quantum (SFQ) pulse pairs to non-return-to-zero (NRZ) encoded voltage signals, the circuitry comprising:
inversion and delay circuitry configured to receive an input signal of SFQ pulses and to provide an inverted and delayed signal by at least one of:
inverting the polarity of the input signal and delaying the inverted signal, or
delaying the input signal and inverting the polarity of the delayed signal; and

current-controlled voltage source circuitry configured to receive and combine the input signal and the inverted and delayed signal to produce an NRZ-encoded output voltage signal.

12. The interface circuitry of claim 11 , wherein the inversion and delay circuitry comprises one or more Josephson transmission lines (JTLs) configured to incur delay to at least one of the input signal or an inverted version of the input signal, and a polarity inverter gate configured to invert SFQ pulses.

13. The interface circuitry of claim 12 , wherein the polarity inverter gate comprises a counter-wound transformer configured to receive a DC flux bias via an inductive coupling.

14. The interface circuitry of claim 12 , wherein the one or more JTLs are configured to collectively incur one-half clock cycle of delay.

15. A superconducting computing system comprising the interface circuitry of claim 11 , RQL circuitry configured to perform computation to produce the RQL-compliant signals and using, at least in part, RQL-compliant input signals comprising opposite-polarity SFQ pulse pairs, and input superconducting circuitry configured to convert NRZ-encoded input voltage signals to the RQL-compliant input signals.

16. A method comprising:
converting a first transition in a non-return-to-zero (NRZ) encoded input voltage signal to a single flux quantum (SFQ) pulse;
reflecting the SFQ pulse to generate an inverted SFQ pulse;
providing a pulse pair comprising the inverted SFQ pulse following the SFQ pulse within same clock cycle as an output signal; and
repeating the reflection and pulse pair provision until a second transition, opposite from the first transition, in the input signal.

17. The method of claim 16 , wherein the first voltage-level transition is from a low voltage to a high voltage.

18. The method of claim 17 , wherein the pulse pair consists of a positive SFQ pulse followed by a negative SFQ pulse one half clock cycle later.

19. A method comprising:
inverting and delaying a reciprocal quantum logic (RQL) encoded input signal consisting of opposite-polarity single flux quantum (SFQ) pulse pairs;
restoring a non-return-to-zero (NRZ) encoded output voltage signal level with the inverted and delayed signal at substantially the same time as the input signal causes the output voltage signal level to transition between binary states; and
repeating the restoring of the output voltage level until the input signal ceases to consist of SFQ pulse pairs for at least one clock cycle.

20. The method of claim 19 , wherein the restoring comprises providing the input signal and the inverted and delayed signal to respective opposite sides of a superconducting current-controlled voltage source comprising one or more superconducting quantum interference devices (SQUIDs).

Assignees

• Herr Quentin P
• Northrop Grumman Systems Corp

Inventors

• Herr Quentin P

Classifications

• H03K19/195 Primary

  using superconductive devices · CPC title

• H03M7/14

  Conversion to or from non-weighted codes · CPC title

• H03M5/02 Primary

  Conversion to or from representation by pulses · CPC title

• G06N99/002

  Physics · mapped topic

• G06N10/20

  Models of quantum computing, e.g. quantum circuits or universal quantum computers · CPC title