Programmable trim filter for successive approximation register analog to digital converter comparator

Patent metadata

Field	Value
Publication number	US-10243579-B2
Application number	US-201715832503-A
Country	US
Kind code	B2
Filing date	Dec 5, 2017
Priority date	Dec 23, 2016
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

The disclosure includes a successive approximation register (SAR) analog to digital converter (ADC). The SAR ADC includes a sampling network to store a sample of an analog signal. The SAR ADC also includes a comparator to successively compare the sample to reference values to determine a digital value corresponding to the sample of the analog signal. The comparator employs a plurality of comparator preamplifiers. The comparator also includes a programmable trim filter. The programmable trim filter is selectively set to adjust a bandwidth of the comparator preamplifiers to a bandwidth value corresponding with a preamplifier settling time subceeding a preamplifier settling threshold.

First claim

We claim:

1. A successive approximation register (SAR) analog to digital converter (ADC) comprising:
a sampling network to store a sample of an analog signal;
a comparator to successively compare the sample to reference values to determine a digital value corresponding to the sample of the analog signal, the comparator including:
a plurality of comparator preamplifiers, and
a programmable trim filter selectively set to adjust a bandwidth of the comparator preamplifiers to a bandwidth value corresponding with preamplifier settling time subceeding a preamplifier settling threshold;

a process monitor to output data indicating a frequency response associated with the comparator preamplifiers to support selectively setting the programmable trim filter based on the determined frequency response, wherein the process monitor includes a ring oscillator of process monitor preamplifiers sharing a common configuration with the comparator preamplifiers, and wherein the process monitor outputs data indicating a frequency response of the ring oscillator as the data indicating the frequency response of the comparator preamplifiers.

2. The SAR ADC of claim 1 , wherein the ring oscillator includes a test filter to support measurement of the frequency response of the ring oscillator.

3. The SAR ADC of claim 1 , wherein the process monitor further includes a frequency division circuit to reduce a frequency of process monitor output to support measurement of the frequency response of the ring oscillator.

4. The SAR ADC of claim 1 , further comprising a processor to:
measure the frequency response associated with the comparator preamplifiers based on the process monitor output data, and
selectively set the programmable trim filter based on the measured frequency response.

5. The SAR ADC of claim 1 , further comprising a memory to store a programmable trim filter setting in a firmware employed by the SAR ADC.

6. The SAR ADC of claim 1 , wherein the programmable trim filter includes a network of capacitors coupled to the comparator preamplifiers and operated via controllable transistors.

7. The SAR ADC of claim 1 , wherein the programmable trim filter operates on a differential signal.

8. The SAR ADC of claim 1 , wherein the comparator includes a latch to store a comparison of the sample and the reference values, the programmable trim filter coupled between the comparator preamplifiers and the latch.

9. A method comprising:
measuring a frequency response of a ring oscillator, the ring oscillator including a plurality of process monitor preamplifiers sharing a common configuration with comparator preamplifiers in a comparator employed by a successive approximation register (SAR) analog to digital converter (ADC);
determining a programmable trim filter setting to adjust a bandwidth of the comparator preamplifiers to a bandwidth value corresponding with preamplifier settling time subceeding a preamplifier settling threshold based on the measured frequency response of the ring oscillator; and
adjusting the bandwidth of the comparator preamplifiers based on the determined programmable trim filter setting.

10. The method of claim 9 , further comprising storing the programmable trim filter setting in a firmware employed during analog to digital conversion.

11. The method of claim 9 , wherein the programmable trim filter setting is employed to control a programmable trim filter in the comparator during conversion of a sample of an analog signal into a digital value, the programmable trim filter including a network of capacitors coupled to the comparator preamplifiers and operated via controllable transistors.

12. The method of claim 11 , wherein the comparator includes a latch to store a comparison of the sample and a reference value, the programmable trim filter coupled between the comparator preamplifiers and the latch.

13. The method of claim 9 , wherein measuring the frequency response of the ring oscillator includes receiving output from a process monitor including the ring oscillator, the output received via a frequency division circuit to reduce a frequency of the process monitor output.

14. A successive approximation register (SAR) analog to digital converter (ADC) comprising:
a comparator including a plurality of comparator preamplifiers and a programmable trim filter;
a process monitor including a ring oscillator of process monitor preamplifiers sharing a common configuration with the comparator preamplifiers; and
a processor to:
measure a frequency response of the ring oscillator, and
determine a programmable trim filter setting for the programmable trim filter to adjust a bandwidth of the comparator preamplifiers to a bandwidth value corresponding with preamplifier settling time subceeding a preamplifier settling threshold based on the measured frequency response of the ring oscillator.

15. The SAR ADC of claim 14 , further comprising memory to store the programmable trim filter setting in a firmware employed during analog to digital conversion.

16. The SAR ADC of claim 14 , wherein the processor is further to employ the programmable trim filter setting to control the programmable trim filter in the comparator during conversion of a sample of an analog signal into a digital value.

17. The SAR ADC of claim 14 , wherein the programmable trim filter includes a network of capacitors coupled to the comparator preamplifiers and operated by the processor via controllable transistors.

18. The SAR ADC of claim 14 , wherein the comparator further includes a latch to store a comparison of a sample of an analog signal and a reference value, the programmable trim filter coupled between the comparator preamplifiers and the latch.

Assignees

• Avnera Corp

Inventors

• Lee Wai
• Link Garry N

Classifications

• H03M1/181

  in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values · CPC title

• H03M1/462 Primary

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/164

  the steps being performed sequentially in series-connected stages (H03M1/161 takes precedence) · CPC title

• H03M1/0626

  by filtering · CPC title

• H03M1/806

  with equally weighted capacitors which are switched by unary decoded digital signals · CPC title