Hybrid phase locked loop having wide locking range

Patent metadata

Field	Value
Publication number	US-10243572-B2
Application number	US-201615364167-A
Country	US
Kind code	B2
Filing date	Nov 29, 2016
Priority date	Mar 23, 2015
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

A digital phased lock loop includes a digital controlled oscillator configured to produce an output signal at an output signal frequency, and a phase comparator configured to compare the output signal or a signal derived from the output signal, with a reference signal at a reference signal frequency or a signal derived from the reference signal to produce a phase error signal. A first loop filter produces a first control signal for the digital controlled oscillator. A frequency error measuring circuit produces a frequency error signal that directly represents a frequency difference between the output signal frequency and the reference signal frequency. A second loop filter produces a second control signal for the digital controlled oscillator from an output of the frequency error measuring circuit. A circuit combines the first and second control signals and providing the combined control signals to the digital controlled oscillator.

First claim

What is claimed is:

1. A digital phased lock loop comprising:
a digital controlled oscillator generating an output signal at an output signal frequency or at a frequency derived from the output signal frequency;
a phase comparator coupled to the digital controlled oscillator and to a reference signal at a reference signal frequency or a signal derived from the reference signal and generating a phase error signal derived from output signal and the reference signal;
a first loop filter configured to produce a first control signal for the digital controlled oscillator from an output of the phase comparator;
a frequency error measuring circuit coupled to the output of the phase comparator to produce a frequency error signal that directly represents a frequency difference between the output signal frequency and the reference signal frequency;
a second loop filter generating a second control signal for the digital controlled oscillator from an output of the frequency error measuring circuit; and
a circuit for combining the first and second control signals and providing the combined control signals to the digital controlled oscillator.

2. The digital phased lock loop of claim 1 , wherein:
the first loop filter comprises a proportional part producing a proportional component of the control signal, an integral part producing an integral component of the control signal, and an adder configured to receive the respective proportional and integral components at first and second inputs thereof to produce the control signal, the integral part including a delayed feedback loop normally configured to accept the integral component at an input thereof; and
the second loop filter comprises a proportional part producing a proportional component of the control signal, an integral part producing an integral component of the control signal, and an adder configured to receive the respective proportional and integral components at first and second inputs thereof to produce the control signal, the integral part including a delayed feedback loop normally configured to accept the integral component at an input thereof.

3. The digital phase locked loop of claim 1 , wherein:
the delayed feedback loop in the first and second loop filters each comprise a unit delay memory.

4. The digital phase locked loop of claim 1 , wherein:
the frequency error measuring circuit is configured to count the number of phase transitions n in a fixed time window having an interval t, the frequency error signal being equal to n/t.

5. The digital phase locked loop of claim 1 , wherein:
the frequency error measuring circuit is configured to determine the periodicity of the phase difference between the output signal and the reference signal, the frequency error signal being equal to the inverse of the determined periodicity.

6. A method of reducing the convergence time in a digital phase locked loop,
comprising:
generating an output signal from a digitally controlled oscillator;
comparing the output signal or a signal derived from the output signal with a reference signal or a signal derived from the reference signal to produce a phase error signal;
filtering the phase error signal in a first loop filter having a proportional part producing a proportional component and an integral part producing an integral component, the integral part including a delayed feedback loop normally receiving at an input thereof the integral component;
applying the proportional and integral components to respective first and second inputs of an adder to produce a first control signal;
comparing the frequency of the output signal with the frequency of the reference signal, or a signal derived therefrom to produce a frequency error signal that directly represents frequency difference between the output signal frequency and the reference signal frequency;
filtering the frequency error signal in a second loop filter having a proportional part producing a proportional component and a integral part producing an integral component, the integral part including a delayed feedback loop normally receiving at an input thereof the integral component; and
combining the first and second control signals and providing the combined control signals to the digital controlled oscillator.

7. The method of claim 6 wherein comparing the frequency of the output signal with the frequency of the reference signal, or a signal derived therefrom comprises:
counting the number of phase transitions n in a fixed time window having an interval t; and
setting the frequency error signal equal to n/t.

8. The method of claim 6 wherein comparing the frequency of the output signal with the frequency of the reference signal, or a signal derived therefrom comprises:
determining the periodicity of the phase difference between the output signal and the reference signal; and
setting the frequency error signal being equal to the inverse of the determined periodicity.

Assignees

• Microsemi Soc Corp

Inventors

• Reddy Prakash

Classifications

• H03L7/0991

  the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814) · CPC title

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H03L7/093 Primary

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/00

  Automatic control of frequency or phase; Synchronisation · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title