Voltage level shifter monitor with tunable voltage level shifter replica circuit

Patent metadata

Field	Value
Publication number	US-10243563-B2
Application number	US-201615394296-A
Country	US
Kind code	B2
Filing date	Dec 29, 2016
Priority date	Dec 29, 2016
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

Embodiments include circuits, apparatuses, and systems for voltage level shifter monitors. In embodiments, a voltage level shifter monitor may include a first signal generator to generate a signal in a first voltage domain, a second signal generator to generate a second signal in a second voltage domain, where the second digital signal corresponds to the first digital signal, a voltage level shifter replica circuit to convert the first digital signal from the first voltage domain to a third digital signal in the second voltage domain, and a comparison circuit to generate a digital error signal based at least in part on the second digital signal and the third digital signal. Other embodiments may be described and claimed.

First claim

What is claimed is:

1. A voltage level shifter monitor comprising:
a first signal generator to generate a first digital signal in a first voltage domain;
a second signal generator to generate a second digital signal in a second voltage domain, wherein the second digital signal corresponds to the first digital signal;
a first voltage level shifter replica circuit to convert the first digital signal from the first voltage domain to a third digital signal in the second voltage domain;
a second voltage level shifter replica circuit to provide a fourth digital signal in the second voltage domain that corresponds to an inverted version of the first digital signal; and
a comparison circuit to:
generate a first digital error signal based at least in part on the second digital signal and the third digital signal; and
generate a second digital error signal based at least in part on the fourth digital signal and an inverted version of the second digital signal.

2. The voltage level shifter monitor of claim 1 , wherein the comparison circuit includes:
a first exclusive or (XOR) gate having a first input terminal to receive the second digital signal and a second input terminal to receive the third digital signal; and
a second XOR gate having a third input terminal to receive the fourth digital signal and a fourth input terminal to receive the inverted version of the second digital signal.

3. The voltage level shifter monitor of claim 1 , wherein the first voltage level shifter replica circuit includes a first contention setting input terminal, the second voltage level shifter replica circuit includes a second contention setting input terminal, the first voltage level shifter replica circuit is to convert the first digital signal to the third digital signal based at least in part on a contention setting signal received at the first contention setting input terminal, and the second voltage level shifter replica circuit is to provide the fourth digital signal based at least in part on the contention setting signal received at the second contention setting input terminal.

4. The voltage level shifter monitor of claim 3 , further comprising a contention setting controller to generate the contention setting signal.

5. The voltage level shifter monitor of claim 1 , wherein the first voltage level shifter replica circuit includes a first inverter having a first variable N-type metal oxide semiconductor (NMOS) transistor and a second inverter having a second variable NMOS transistor.

6. The voltage level shifter monitor of claim 5 , wherein the first variable NMOS transistor includes a first programmable set of fingers set by a contention setting signal and the second variable NMOS transistor includes a second programmable set of fingers set by the contention setting signal.

7. A voltage level shifter monitor comprising:
a first signal generator to generate a first digital signal in a first voltage domain;
a second signal generator to generate a second digital signal in a second voltage domain, wherein the second digital signal corresponds to the first digital signal;
a voltage level shifter replica circuit to convert the first digital signal from the first voltage domain to a third digital signal in the second voltage domain; and
a comparison circuit to generate a digital error signal based at least in part on the second digital signal and the third digital signal,
wherein the first signal generator includes a first signal generation circuit and a first flip flop, the second signal generator includes a second signal generation circuit and a second flip flop, and the comparison circuit includes an XOR gate and a third flip flop.

8. An integrated circuit comprising:
a first digital circuit in a first operating voltage domain;
a second digital circuit in a second operating voltage domain;
a voltage level shifter to convert a digital signal from the first operating voltage domain to the second operating voltage domain; and
a voltage level shifter monitor having one or more error signal output terminals to warn of a possible operating error of the voltage level shifter, wherein the voltage level shifter monitor includes a voltage level shifter replica circuit with one or more variable transistors.

9. The integrated circuit of claim 8 , further comprising control logic coupled with the one or more error signal output terminals, the control logic to alter one or more of an operating voltage or an operating frequency of the first digital circuit in response to one or more of the one or more error signal output terminals indicates a warning of possible operating error of the voltage level shifter.

10. The integrated circuit of claim 9 , wherein the voltage level shifter monitor is a first voltage level shifter monitor to detect contention effect failure of the voltage level shifter and the integrated circuit further comprises a second voltage level shifter monitor to detect propagation delay in the voltage level shifter.

11. The integrated circuit of claim 8 , wherein the one or more variable transistors include a first variable N-type metal oxide semiconductor (NMOS) transistor and a second variable NMOS transistor, wherein the voltage level shifter replica circuit includes a first inverter having the first variable NMOS transistor and a second inverter having the second variable NMOS transistor.

12. The integrated circuit of claim 11 , wherein the first variable NMOS transistor includes a first programmable set of fingers set by a contention setting signal and the second variable NMOS transistor includes a second programmable set of fingers set by the contention setting signal.

13. The integrated circuit of claim 12 , further comprising a contention setting controller to generate the contention setting signal.

Assignees

• Intel Corp

Inventors

• Bonetti Andrea
• Kulkarni Jaydeep P
• Tokunaga Carlos
• Cho Minki
• Meinerzhagen Pascal A
• Khellah Muhammad M

Classifications

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• H03K19/018521 Primary

  of complementary type, e.g. CMOS · CPC title