Stepped attenuation circuit with constant decibel steps

Patent metadata

Field	Value
Publication number	US-10243530-B1
Application number	US-201715582620-A
Country	US
Kind code	B1
Filing date	Apr 29, 2017
Priority date	Apr 29, 2017
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

An attenuation circuit with stages having constant dB steps between stages is provided. The attenuation circuit can be configured as a ladder network using resistors having three different values. A first resistor can be connected between the last stage of the attenuation circuit and ground and have a first predetermined resistance. One or more second resistors can be connected in each stage and have a second predetermined resistance based on the first predetermined resistance and the dB step between stages. One or more third resistors can be connected in parallel to the first resistor for the remaining stages and have a third predetermined resistance based on the first predetermined resistance and the dB step between stages.

First claim

What is claimed is:

1. An attenuation circuit for an electronic device comprising:
a voltage source ( 104 ); and
a ladder network ( 65 ) having a first end (associated with V 0 ) and a second end (associated with V k ) opposite the first end (V 0 ), the first end (V 0 ) of the ladder network ( 65 ) being connected to the voltage source ( 104 ), the ladder network comprising:
a first stage (stage k) positioned at the second end (V k ) of the ladder network ( 65 ), the first stage (stage k) comprising a first resistor (R 1 ) connected to a second resistor (R 2 ), wherein the first resistor (R 1 ) has a first resistance value (Rbase) and the second resistor (R 2 ) has a second resistance value (Rh);
a plurality of second stages (stages 1 to k− 1 ) connected between the first end (V 0 ) of the ladder network ( 65 ) and the first stage (stage k), each second stage of the plurality of second stages (stages 1 to k− 1 ) comprising a third resistor (R 5 ) connected to a fourth resistor (R 6 ), wherein the third resistor (R 5 ) has a third resistance value (Rv) and the fourth resistor (R 6 ) has a fourth resistance value (Rh) equal to the second resistance value (Rh); and
wherein the second resistance value (Rh) is different from the first resistance value (Rbase), the third resistance value (Rv) is different from the first resistance value (Rbase) and the second resistance value (Rh), and wherein the first resistance value (Rbase) is selected to obtain a predetermined characteristic for the attenuation circuit, the predetermined characteristic corresponding to at least one of power dissipation, noise or bandwidth.

2. The attenuation circuit of claim 1 , further comprising a plurality of taps, each tap of the plurality of taps corresponding to a voltage step for the attenuation circuit, and wherein the first stage and the plurality of second stages are configured to provide an equal decibel (dB) step between the plurality of taps.

3. The attenuation circuit of claim 2 , wherein the first resistor and the second resistor of the first stage are connected to a tap of the plurality of taps and the third resistor and the fourth resistor of each second stage of the plurality of second stages are connected to a corresponding tap of the plurality of taps.

4. The attenuation circuit of claim 3 , wherein the second resistor is connected to the corresponding tap of one second stage of the plurality of second stages.

5. The attenuation circuit of claim 1 , wherein the third resistor of each second stage of the plurality of second stages is connected in parallel to the first resistor.

6. The attenuation circuit of claim 1 , wherein the first resistor and the second resistor of the first stage are connected in an L configuration and the third resistor and the fourth resistor for each second stage of the plurality of second stages are connected in an L configuration.

7. A method for configuring an attenuation circuit ( 65 ) having a first stage (stage k) connected to a plurality of second stages (stages 1 to k− 1 ), the first stage (stage k) comprising a first resistor (R 1 ) connected to a second resistor (R 2 ) and each second stage of the plurality of second stages (stages 1 to k− 1 ) comprising a third resistor (R 5 ) connected to a fourth resistor (R 6 ), the method comprising:
selecting a first resistance value (Rbase) for the first resistor (R 1 );
selecting a decibel (dB) step to be obtained between stages (stages 1 to k) of the attenuation circuit ( 65 );
calculating a second resistance value (Rh) for the second resistor (R 2 ) and the fourth resistor (R 6 ) based on the first resistance value (Rbase) and the selected dB step;
calculating a third resistance value (Rv) for the third resistor (R 5 ) based on the first resistance value (Rbase) and the selected dB step;
selecting a number of stages for the plurality of second stages (stages 1 to k− 1 ); and
assembling the attenuation circuit ( 65 ) to have the first stage (stage k) connected to the selected number of second stages (stages 1 to k− 1 ), the first stage (stage k) having the first resistor (R 1 ) with the first resistance value (Rbase) and the second resistor (R 2 ) with the second resistance value (Rh), each second stage of the plurality of second stages (stages 1 to k− 1 ) having the third resistor (R 5 ) with the third resistance value (Rv) and the fourth resistor (R 6 ) with the second resistance value (Rh).

8. The method of claim 7 , wherein the assembling the attenuation circuit includes connecting the first stage and the selected number of second stages in a ladder network.

9. The method of claim 7 , wherein the assembling the attenuation circuit includes:
connecting the first resistor and the second resistor of the first stage in an L configuration; and
connecting the third resistor and the fourth resistor of each second stage of the selected number of second stages in an L configuration.

10. The method of claim 9 , wherein the connecting the third resistor and the fourth resistor includes connecting the third resistor in parallel to the first resistor.

11. The method of claim 7 , wherein the assembling the attenuation circuit includes:
providing a plurality of taps;
connecting the first resistor and the second resistor of the first stage to a tap of the plurality of taps; and
connecting the third resistor and the fourth resistor of each second stage of the selected number of second stages to a respective tap of the plurality of taps.

12. The method of claim 11 , wherein the assembling the attenuation circuit includes connecting each tap of the plurality of taps to a corresponding connection point of a plurality of connection points on a switch, the switch being configured to permit a selection of a connection point of the plurality of connection points to provide a connection between a corresponding tap of the plurality of taps connected to the selected connection point and another device connected to the switch.

13. An amplifier module ( 63 ) comprising:
an operational amplifier ( 92 ), the operational amplifier ( 92 ) having a first input configured to be connected to a voltage source ( 112 );
an attenuation circuit ( 65 ) connected to an output of the operational amplifier ( 92 ), the attenuation circuit ( 65 ) comprising:
a first stage (stage k) comprising a first resistor (R 1 ) connected to a second resistor (R 2 ), the first resistor (R 1 ) having a first resistance value (Rbase) and the second resistor (R 2 ) having a second resistance value (Rh);
a plurality of second stages (stages 1 to k− 1 ) connected to the first stage (stage k), each second stage of the plurality of second stages (stages 1 to k− 1 ) comprising a third resistor (R 5 ) connected to a fourth resistor (R 6 ), wherein the third resistor (R 5 ) has a third resistance value (Rv) and the fourth resistor (R 6 ) has a fourth resistance value (Rh) equal to the second resistance value (Rh), wherein one second stage (stage 1 ) of the plurality of second stages (stages 1 to k− 1 ) being connected to the output of the operational amplifier ( 92 );
a plurality of taps (V 0 -V 7 ), each tap of the plurality of taps (V 0 -V 7 ) corresponding to a voltage step for the attenuation circuit ( 65 ); and
wherein the first resistance value (Rbase), the second resistance value (Rh) and the third resistance value (Rv) are selected to provide a predetermined decibel (dB) step between the plurality of taps (V 0 -V 7 ); and

a switch ( 110 ) connected between the attenuation circuit ( 65 ) and a second input of the operational amplifier ( 92 ), the switch ( 110 ) having a plurality of connection points (s 1 -s 8 ),

Assignees

• Adtran Inc

Inventors

• Joffe Daniel M

Classifications

• H03F3/45475 Primary

  using IC blocks as the active amplifying circuit · CPC title

• H03F2203/45528

  the FBC comprising one or more passive resistors and being coupled between the LC and the IC · CPC title

• H03G1/0088

  using discontinuously variable devices, e.g. switch-operated · CPC title

• H03G2201/106

  being attenuating element · CPC title

• H03G3/30 Primary

  in amplifiers having semiconductor devices · CPC title