Single input, dual output path low-noise amplifier

Patent metadata

Field	Value
Publication number	US-10243518-B2
Application number	US-201715696891-A
Country	US
Kind code	B2
Filing date	Sep 6, 2017
Priority date	Sep 12, 2016
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

The present disclosure is directed to a dual output path LNA that can be used to break the tradeoff between the output impedance and linearity of an LNA without the problems of a programmable output impedance LNA. In an embodiment, the dual output path architecture includes an LNA driving a low level of impedance in a low voltage gain path, thus achieving high linearity in the presence of large blockers, and driving a high level of impedance in a high voltage gain path to increase the LNA's voltage gain and minimize performance degradation due to a noisier, low power receiver front-end chain following the LNA. The present disclosure is further directed to a local oscillator (LO) offset circuit with low power and reduced spur generation.

First claim

What is claimed is:

1. A front-end receiver comprising:
a low-noise amplifier (LNA) configured to provide an amplified signal;
a first output path of the LNA comprising a first isolation circuit and a first impedance circuit;
a second output path of the LNA comprising a second isolation circuit and a second impedance circuit; and
a circuit component coupled to both the first output path of the LNA and the second output path of the LNA and configured to receive the amplified signal from the LNA through one of the first output path of the LNA and the second output path of the LNA based on a current power mode of the front-end receiver,
wherein the second impedance circuit provides a larger voltage gain for the LNA than the first impedance circuit, and
wherein the second impedance circuit has a higher impedance than the first impedance circuit.

2. The front-end receiver of claim 1 , wherein the first isolation circuit is configured to isolate the LNA from the first impedance circuit and the second isolation circuit is configured to isolate the LNA from the second impedance circuit.

3. The front-end receiver of claim 2 , wherein the first isolation circuit is a first cascode circuit and the second isolation circuit is a second cascode circuit.

4. The front-end receiver of claim 2 , further comprising a control circuit configured to control the first isolation circuit and the second isolation circuit based on the current power mode.

5. The front-end receiver of claim 1 , wherein the circuit component is configured to receive the amplified signal from the LNA through the second output path of the LNA based on the current power mode being a low-power mode.

6. The front-end receiver of claim 1 , wherein the circuit component is a mixer, a filter, or an analog-to-digital converter.

7. A method comprising:
determining a current power mode of a front-end receiver;
based on the current power mode being determined to not be a low-power mode, turning on a first output path of a low-noise amplifier (LNA) and turning off a second output path of the LNA; and
based on the current power mode being determined to be the low-power mode, turning on the second output path of the LNA and turning off the first output path of the LNA,
wherein the second output path of the LNA provides a larger voltage gain for the LNA than the first output path of the LNA, and
wherein the second output path of the LNA presents a higher impedance to the LNA than the first output path of the LNA.

8. The method of claim 7 , wherein both the first output path of the LNA and the second output path of the LNA are configured to provide an amplified output signal from the LNA to a circuit component when turned-on.

9. The method of claim 8 , wherein the circuit component is a mixer, a filter, or an analog-to-digital converter.

10. The method of claim 7 , wherein the first output path of the LNA comprises a first isolation circuit and a first impedance circuit, and wherein the second output path of the LNA comprises a second isolation circuit and a second impedance circuit.

11. The method of claim 10 , wherein the first isolation circuit is a first cascode circuit and the second isolation circuit is a second cascode circuit.

12. The method of claim 10 , wherein the first isolation circuit is configured to isolate the LNA from the first impedance circuit when the first output path of the LNA is turned-off, and wherein the second isolation circuit is configured to isolate the LNA from the second impedance circuit when the second output path of the LNA is turned-off.

13. A front-end receiver comprising:
a low-noise amplifier (LNA) configured to provide an amplified signal;
a first output path of the LNA comprising a first impedance circuit;
a second output path of the LNA comprising a second impedance circuit;
a circuit component coupled to both the first output path of the LNA and the second output path of the LNA and configured to receive the amplified signal from the LNA through one of the first output path of the LNA and the second output path of the LNA based on a current power mode of the front-end receiver; and
a control circuit configured to turn-on or turn-off the first output path of the LNA and the second output path of the LNA based on the current power mode,
wherein the second impedance circuit provides a larger voltage gain for the LNA than the first impedance circuit, and
wherein the second impedance circuit has a higher impedance than the first impedance circuit.

14. The front-end receiver of claim 13 , wherein the control circuit is configured to turn-on the first output path of the LNA and turn-off the second output path of the LNA based on the current power mode of the front-end receiver being a high power mode.

15. The front-end receiver of claim 13 , wherein the control circuit is configured to turn-on the second output path of the LNA and turn-off the first output path of the LNA based on the current power mode of the front-end receiver being a low power mode.

16. The front-end receiver of claim 13 , wherein the first output path of the LNA is configured to isolate the LNA from the first impedance circuit based on the current power mode of the receiver front-end being a low power mode.

17. The front-end receiver of claim 13 , wherein the second output path of the LNA is configured to isolate the LNA from the second impedance circuit based on the current power mode of the receiver front-end being a high power mode.

18. The method of claim 10 , wherein the second impedance circuit has a higher impedance than the first impedance circuit.

19. The front-end receiver of claim 1 , wherein the first isolation circuit includes a first transistor and a second transistor, and wherein a drain of the first transistor is directly connected to a drain of the second transistor.

20. The front-end receiver of claim 1 , wherein the second isolation circuit includes a first transistor and a second transistor, and wherein a drain of the first transistor is directly connected to a drain of the second transistor.

Assignees

• Avago Tech Int Sales Pte Lid

Inventors

• Torre Valentina Della
• Anand Seema B
• CHI Howard
• Conta Matteo

Classifications

• H04B1/40

  Circuits · CPC title

• H04B1/10 Primary

  Means associated with receiver for limiting or suppressing noise or interference · CPC title

• H03F1/223

  with MOSFET's · CPC title

• H04B2001/0491

  with frequency synthesizers, frequency converters or modulators · CPC title

• H03F2200/333

  A frequency modulator or demodulator being used in the amplifier circuit · CPC title