Solar cell and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10243090-B2
Application number	US-201514734870-A
Country	US
Kind code	B2
Filing date	Jun 9, 2015
Priority date	Jun 10, 2014
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

Discussed is a method for manufacturing a solar cell. The method includes forming a tunneling layer on a semiconductor substrate; forming a semiconductor layer on the tunneling layer, wherein the forming of the semiconductor layer including depositing a semiconductor material; and forming an electrode connected to the semiconductor layer. The tunneling layer is formed under a temperature higher than room temperature and a pressure lower than atmospheric pressure.

First claim

What is claimed is:

1. A method for manufacturing a solar cell, the method comprising:
forming a tunneling layer on a semiconductor substrate;
forming a semiconductor layer on the tunneling layer, wherein the forming of the semiconductor layer includes depositing a semiconductor material;
forming a capping layer on the semiconductor layer; and
forming an electrode connected to the semiconductor layer,
wherein the tunneling layer is formed under a temperature higher than room temperature and a pressure lower than atmospheric pressure,
wherein a pressure of the forming of the semiconductor layer is smaller than the pressure of the forming of the tunneling layer,
wherein the forming of the semiconductor layer further comprises doping the semiconductor layer with dopants,
wherein the capping layer is formed between the forming of the semiconductor layer and the forming of the electrode, and
wherein the forming of the tunneling layer, the forming of the semiconductor layer, and the forming of the capping layer are performed by an in-situ process continuously performed in a same apparatus.

2. The method according to claim 1 , wherein the semiconductor layer comprises:
a first conductive type region comprising a first conductive type dopant;
a second conductive type region comprising a second conductive type dopant different from the first conductive type dopant; and
a barrier region between the first conductive type region and the second conductive type region,
wherein the first conductive type region, the second conductive type region, and the barrier region are on the tunneling layer.

3. The method according to claim 1 , wherein, in the forming of the tunneling layer, the temperature is in a range from about 600° C. to about 800° C. and the pressure is in a range from about 0.01 Torr to about 2 Torr.

4. The method according to claim 1 , wherein the forming of the tunneling layer is performed for about 5 minutes to about 30 minutes.

5. The method according to claim 1 , wherein the forming of the tunneling layer is performed under an atmosphere including an oxygen gas, and
the tunneling layer comprises an oxide.

6. The method according to claim 5 , wherein the tunneling layer comprises a thermal oxidation layer formed by a thermal oxidation process.

7. The method according to claim 5 , wherein the atmosphere of the forming of the tunneling layer further comprises a nitrogen gas and a chlorine gas.

8. The method according to claim 1 , wherein the tunneling layer has a thickness of about 1.0 nm to about 1.5 nm.

9. The method according to claim 1 , wherein the forming of the tunneling layer, the forming of the semiconductor layer, and the forming of the capping layer are performed at a low pressure chemical vapor deposition apparatus.

10. The method according to claim 1 , wherein the forming of the tunneling layer and the forming of the semiconductor layer are performed under different atmospheres.

11. The method according to claim 10 , wherein the forming of the tunneling layer is performed under an atmosphere including an oxygen gas, and
the forming of the semiconductor layer is performed under an atmosphere including a gas including silicon.

12. The method according to claim 1 , wherein a difference between the temperature of the forming of the tunneling layer and a temperature of the forming of the semiconductor layer is 200° C. or less.

13. The method according to claim 1 , wherein the pressure of the forming of the tunneling layer is in a range of about 0.01 Torr to about 2 Torr, and
the pressure of the forming of the semiconductor layer is in a range of about 0.01 Ton to about 0.5 Torr.

14. The method according to claim 13 , wherein the semiconductor layer is thicker than the tunneling layer.

15. The method according to claim 1 , further comprising:
heat-treating the semiconductor layer for an activation between the forming of the capping layer and the forming of the electrode, and
wherein the forming of the tunneling layer, the forming of the semiconductor layer, the forming of the capping layer, and the heat-treating are performed by an in-situ process continuously performed in the same apparatus.

16. A solar cell manufactured by the method according to claim 1 , wherein the tunneling layer of the solar cell has a thickness of about 2 nm or less.

17. The method according to claim 1 , wherein the capping layer includes silicon oxide, and has a thickness of about 50 nm to 100 nm.

18. The method according to claim 1 , wherein the capping layer is thicker than the tunneling layer.

Assignees

• Lg Electronics Inc

Inventors

• Yang Youngsung
• Choi Junghoon
• Park Changseo
• Kwon Hyungjin

Classifications

• Y02E10/547

  Monocrystalline silicon PV cells · CPC title

• H01L31/0745

  Electricity · mapped topic

• H01L31/1864

  Electricity · mapped topic

• Y02P70/521

  Cross-Sectional Technologies · mapped topic

• H01L31/02167

  Electricity · mapped topic