Extended platform with additional memory module slots per CPU socket

Patent metadata

Field	Value
Publication number	US-10242717-B2
Application number	US-201715808390-A
Country	US
Kind code	B2
Filing date	Nov 9, 2017
Priority date	Sep 30, 2016
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board that includes a first row of elements including a first CPU positioned between first and second groups of dual in-line memory modules (DIMMs). The printed circuit board also includes a second row of elements including a second CPU positioned between third and fourth groups of DIMMs. The apparatus also includes a third row of elements including a fifth group of DIMMs, wherein the second row of elements is positioned between the first row of elements and the third row of elements. Other embodiments are described and claimed.

First claim

What is claimed:

1. An apparatus comprising:
a printed circuit board including first, second, and third rows of elements;
the first row of elements including a first central processing unit (CPU) socket configured to receive a first CPU and a first memory region configured to receive at least eight memory modules, the at least eight memory modules of the first memory region to couple with the first CPU via a first group of high speed input/output (HSIO) links;
the second row of elements including a second memory region and a third memory region, the second and third memory regions to separately receive at least eight memory modules, the first CPU socket position between the first and second memory regions, the at least eight memory modules of the second memory region to couple with the first CPU via a second group of HSIO links; and
the third row of elements including a second CPU socket configured to receive a second CPU and a fourth memory region configured to receive at least eight memory modules, the second CPU socket positioned between the third and fourth memory regions, the at least eight memory modules of the third memory region to couple with the second CPU via a third group of HSIO links, the at least eight memory modules of the fourth memory region to couple with the second CPU via a fourth group of HSIO links.

2. The apparatus of claim 1 , comprising the first, second, third and fourth groups of HSIO links separately including at least two HSIO links.

3. The apparatus of claim 2 , comprising:
the first and the second groups of HSIO links to couple memory modules of respective first and second memory regions with the first CPU through first high speed serial interfaces at the first CPU; and
the third and the fourth groups of HSIO links to couple memory modules of respective third and fourth memory regions with the second CPU through second high speed serial interfaces at the second CPU.

4. The apparatus of claim 2 , comprising the first, second, third and fourth groups of HSIO links separately capable of a data transfer rate of at least 50 gigabits per second per pin.

5. The apparatus of claim 1 , the first, second, third and fourth memory regions configured to separately receive at least eight memory modules comprises the at least eight memory modules including dual in-line memory modules (DIMMs).

6. The apparatus of claim 5 , comprising the DIMMs included in the at least eight memory modules including volatile memory or non-volatile memory.

7. The apparatus of claim 6 , the volatile memory comprising dynamic random access memory.

8. The apparatus of claim 6 , the non-volatile memory comprising three dimensional crosspoint memory, magnetoresistive random access memory (MRAM), ferrorelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, polymer memory or ferroelecric transistor random access memory (FeTRAM).

9. A method comprising:
positioning a first central processing unit (CPU) socket between first and second memory regions of a printed circuit board, the first and second memory regions configured to separately accept at least eight memory modules;
positioning a second CPU socket between third and fourth memory regions of the printed circuit board, the third and fourth memory regions configured to separately accept at least eight memory modules;
coupling the first CPU socket to the at least eight memory modules of the first and second memory regions via respective first group and second group of high speed input/output (HSIO) links; and
coupling the second CPU socket to the at least eight memory modules of the third and fourth memory regions via respective third group and fourth group of HSIO links.

10. The method of claim 9 , comprising the first, second, third and fourth groups of HSIO links separately including at least two HSIO links.

11. The method of claim 10 , comprising:
coupling the first and the second groups of HSIO links to memory modules of respective first and second memory regions with the first CPU through first high speed serial interfaces at the first CPU; and
coupling the third and the fourth groups of HSIO links to memory modules of respective third and fourth memory regions with the second CPU through a second high speed serial interfaces at the second CPU.

12. The method of claim 10 , comprising the first, second, third and fourth groups of HSIO links separately capable of a data transfer rate of at least 50 gigabits per second per pin.

13. The method of claim 9 , the first, second, third and fourth memory regions to separately accept at least eight memory modules comprises the at least eight memory modules accepting dual in-line memory modules (DIMMs).

14. The method of claim 13 , comprising the DIMMs included in the at least eight memory modules including volatile memory or non-volatile memory.

15. A system comprising:
a printed circuit board (PCB);
a first row of elements on the printed circuit board, including a first central processing unit (CPU) coupled with a first group of at least eight dual inline memory modules (DIMMs) via a first group of high speed input/output (HSIO) links;
a second row of elements on the printed circuit board, including second and third groups each having at least eight DIMMs, the first CPU position between the first and second groups of DIMMs, the second group of DIMMs coupled with the first CPU via a second group of HSIO links; and
a third row of elements on the printed circuit board, including a second CPU and a fourth group of at least eight DIMMs, the second CPU positioned between the third and fourth groups of DIMMs, the third and fourth groups of DIMMs coupled with the second CPU via respective third and fourth groups of HSIO links.

16. The system of claim 15 , comprising the first, second, third and fourth groups of HSIO links separately including at least two HSIO links.

17. The system of claim 15 , wherein:
the first and the second groups of HSIO links to couple memory modules of respective first and second memory regions with the first CPU through first high speed serial interfaces at the first CPU; and
the third and the fourth groups of HSIO links to couple memory modules of respective third and fourth memory regions with the second CPU through second high speed serial interfaces at the second CPU.

18. The system of claim 15 , comprising the first, second, third and fourth groups of HSIO links separately capable of a data transfer rate of at least 50 gigabits per second per pin.

19. The system of claim 15 , comprising the first, second, third and fourth groups of DIMMs including volatile memory that includes dynamic random access memory.

20. The system of claim 15 , comprising the first, second, third and fourth groups of DIMMs including volatile memory and non-volatile memory.

21. The system of claim 20 , the volatile memory comprising dynamic random access memory.

22. The system of claim 20 , the non-volatile memory comprising three dimensional crosspoint memory, magnetoresistive random access memory (MRAM), ferrorelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, polymer memory or ferroelecric transistor random access memory (FeTRAM).

Assignees

• Intel Corp

Inventors

• Querbach Bruce
• Vogt Pete D

Classifications

• G11C5/04 Primary

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• H05K2201/10159

  Memory · CPC title

• H05K2201/09409

  Multiple rows of pads, lands, terminals or dummy patterns; Multiple rows of mounted components · CPC title

• H05K1/0295

  adapted for choosing between different types or different locations of mounted components · CPC title