Reconfigurable graphics processor for performance improvement

Patent metadata

Field	Value
Publication number	US-10242652-B2
Application number	US-201514959455-A
Country	US
Kind code	B2
Filing date	Dec 4, 2015
Priority date	Jun 13, 2013
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

Power gating a portion of a graphics processor may be used to improve performance or to achieve a power budget. A processor granularity, such as a slice or subslice, may be gated.

First claim

What is claimed is:

1. A graphics processor comprising:
a memory;
an interface logic;
first and second independently power gateable portions of the graphics processor, said first and second independently power gateable portions in different clock domains; and
first logic to power gate a first portion and not the second portion of the graphics processor so that said first portion is powered on and said second portion is powered off; and
second logic to implement clock gating of the first portion without power gating said first portion, said second logic to clock gate the first portion without affecting the clock frequency of the second portion and said second logic to change a clock frequency of at least one of said power gateable portions in response to a determination that power gating is not an option for said one of said power gateable portions, wherein power gating is not an option because savings achieved by power gating do not exceed power cost arising from a corresponding frequency increase caused by power gating.

2. The processor of claim 1 wherein one of said portions is a processor core.

3. The processor of claim 2 wherein both of said portions are processor cores.

4. The processor of claim 1 including a power controller.

5. The processor of claim 1 including a plurality of separate, identical processing units.

6. The processor of claim 5 wherein said processing units are independently power gated.

7. One more non-transitory computer readable media storing instructions to perform a sequence comprising:
determining that power gating is not an option for a first independently power gateable portion of a graphics processor, said graphics processor also including a second independently power gateable portion, wherein power gating is not an option because savings achieved by power gating do not exceed power cost arising from a corresponding frequency increase caused by power gating; and
implementing clock gating of the first independently power gateable portion without affecting the clock frequency of the second independently power gateable portion in response to said determination.

8. The media of claim 7 , further storing instructions to perform a sequence wherein one of said portions is a processor core.

9. The media of claim 8 , further storing instructions to perform a sequence wherein both of said portions are processor cores.

10. The media of claim 9 , further storing instructions to perform a sequence including a power controller.

11. The media of claim 10 , further storing instructions to perform a sequence including a plurality of separate, identical processing units.

12. The media of claim 11 , further storing instructions to perform a sequence wherein said processing units are independently power gated.

13. A method comprising:
determining that power gating is not an option for a first independently power gateable portion of a graphics processor, said graphics processor also including a second independently power gateable portion, wherein power gating is not an option because savings achieved by power gating do not exceed power cost arising from a corresponding frequency increase caused by power gating; and
implementing clock gating of the first independently power gateable portion without affecting the clock frequency of the second independently power gateable portion in response to said determination.

14. The method of claim 13 wherein one of said portions is a processor core.

15. The method of claim 14 wherein both of said portions are processor cores.

16. The method of claim 15 including a power controller.

17. The method of claim 16 including a plurality of separate, identical processing units.

18. The method of claim 17 wherein said processing units are independently power gated.

Assignees

• Intel Corp

Inventors

• Kaburlasos Nikos
• Samson Eric C

Classifications

• G06F1/3265 Primary

  Power saving in display device · CPC title

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G09G5/363

  Graphics controllers · CPC title

• G09G2360/06

  Use of more than one graphics processor to process data before displaying to one or more screens · CPC title