Pixel compensation circuit, organic light-emitting display panel and organic light-emitting display device thereof

Patent metadata

Field	Value
Publication number	US-10242622-B2
Application number	US-201815865541-A
Country	US
Kind code	B2
Filing date	Jan 9, 2018
Priority date	Sep 29, 2017
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

A pixel compensation circuit, an organic light-emitting display panel and an organic light-emitting display device are provided. The pixel compensation circuit includes a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a fifth switch transistor, a sixth switch transistor, a light-emitting element, a seventh switch transistor, a storage capacitor, and a drive transistor. The first switch transistor, the fourth switch transistor, and the fifth switch transistor provide a signal on a reference voltage signal terminal to a first node and provide a threshold voltage to a gate of the drive transistor. The second switch transistor and the third switch transistor couple a signal on a first power supply terminal in real time to the gate of the drive transistor. A driving current generated by the drive transistor is protected from adverse effects caused by IR Drop on the first power supply terminal.

First claim

What is claimed is:

1. A pixel compensation circuit, comprising:
a first switch transistor for providing a signal on a reference voltage signal terminal to a first electrode of a drive transistor under a control of a first scan signal terminal, wherein the first switch transistor includes a first electrode and a second electrode, and the second electrode is connected to the first electrode of the drive transistor;
a second switch transistor for providing a signal on a first power supply terminal to the first electrode of the drive transistor under a control of a first light-emitting control signal supplied by a first light-emitting control signal terminal;
a third switch transistor for conducting the first electrode of the drive transistor and a first node under the control of the first light-emitting control signal supplied by the first light-emitting control signal terminal, wherein the third switch transistor includes a first electrode connected to the first electrode of the drive transistor;
a fourth switch transistor for providing a signal on a data signal terminal to the first node under the control of the first scan signal terminal, wherein the fourth switch transistor includes a first electrode and a second electrode, and the second electrode is connected to the first node;
a fifth switch transistor for conducting a gate of the drive transistor and a second electrode of the drive transistor under the control of the first scan signal terminal;
a sixth switch transistor for providing a signal on an initialization signal terminal to the gate of the drive transistor under a control of a second scan signal terminal;
a light-emitting element having a first terminal and a second terminal, the second terminal being connected to a second power supply terminal;
a seventh switch transistor for providing a driving current generated by the drive transistor to the light-emitting element under a control of a second light-emitting control signal supplied by a second light-emitting control signal terminal to drive the light-emitting element to emit light, wherein the second light-emitting control signal is different from the first light-emitting control signal;
a storage capacitor for coupling a voltage on the first node to the gate of the drive transistor when floated; and
the drive transistor for generating the driving current under a control of a voltage difference between the gate and the first electrode.

2. The pixel compensation circuit according to claim 1 , further including:
an eighth switch transistor for providing the signal on the initialization signal terminal to the first terminal of the light-emitting element under a control of a reset control signal terminal.

3. The pixel compensation circuit according to claim 2 , wherein:
the reset control signal terminal and the first scan signal terminal are a same signal terminal; or
the reset control signal terminal and the second scan signal terminal are a same signal terminal; or
the reset control signal terminal and the first light-emitting control signal terminal are a same signal terminal; or
the reset control signal terminal and the second light-emitting control signal terminal are a same signal terminal.

4. The pixel compensation circuit according to claim 2 , wherein:
a gate of the eighth switch transistor is connected to the reset control signal terminal;
a first electrode of the eighth switch transistor is connected to the initialization signal terminal; and
a second electrode of the eighth switch transistor is connected to the first terminal of the light-emitting element.

5. The pixel compensation circuit according to claim 2 , wherein:
the eighth switch transistor is a P-type transistor; or
the eighth switch transistor is an N-type transistor.

6. The pixel compensation circuit according to claim 1 , wherein:
a gate of the first switch transistor is connected to the first scan signal terminal, and
the first electrode of the first switch transistor is connected to the reference voltage signal terminal;
a gate of the second switch transistor is connected to the first light-emitting control signal terminal,
a first electrode of the second switch transistor is connected to the first power supply terminal, and
a second electrode of the second switch transistor is connected to the first electrode of the drive transistor;
a gate of the third switch transistor is connected to the first light-emitting control signal terminal, and
a second electrode of the third switch transistor is connected to the first node;
a gate of the fourth switch transistor is connected to the first scan signal terminal, and
the first electrode of the fourth switch transistor is connected to the data signal terminal;
a gate of the fifth switch transistor is connected to the first scan signal terminal,
a first electrode of the fifth switch transistor is connected to the second electrode of the drive transistor, and
a second electrode of the fifth switch transistor is connected to the gate of the drive transistor;
a gate of the sixth switch transistor is connected to the second scan signal terminal,
a first electrode of the sixth switch transistor is connected to the initialization signal terminal, and
a second electrode of the sixth switch transistor is connected to the gate of the drive transistor;
a gate of the seventh switch transistor is connected to the second light-emitting control signal terminal,
a first electrode of the seventh switch transistor is connected to the second electrode of the drive transistor, and
a second electrode of the seventh switch transistor is connected to the first terminal of the light-emitting element; and
a first terminal of the storage capacitor is connected to the first node, and
a second terminal of the storage capacitor is connected to the gate of the drive transistor.

7. The pixel compensation circuit according to claim 1 , wherein:
the first switch transistor, the second switch transistor, the third switch transistor, the fourth switch transistor, the fifth switch transistor, the sixth switch transistor, and the seventh switch transistor are P-type transistors.

8. The pixel compensation circuit according to claim 1 , wherein:
types of the first switch transistor, the fourth switch transistor and the fifth switch transistor are the same.

9. The pixel compensation circuit according to claim 1 , wherein:
types of the second switch transistor and the third switch transistor are the same.

10. The pixel compensation circuit according to claim 1 , wherein:
the fifth switch transistor is a double gate structure.

11. The pixel compensation circuit according to claim 10 , wherein:
a width of a channel region in an active layer of the fifth switch transistor is in a range of approximately 2.5 μm-3.5 μm; and
a length of the channel region in the active layer of the fifth switch transistor is in a range of approximately 6 μm-8 μm.

12. The pixel compensation circuit according to claim 1 , wherein:
the sixth switch transistor is a double gate structure.

13. The pixel compensation circuit according to claim 12 , wherein:
a width of a channel region in an active layer of the sixth switch transistor is in a range of approximately 2.5 μm-3.5 μm; and
a length of the channel region in the active layer of the sixth switch transistor is in a range of approximately 6 μm-8 μm.

14. The pixel compensation circuit according to claim 1 , wherein:
any of the first switch transistor, the second switch transistor, the third switch transistor, the fourth switch transistor, the fifth switch transistor, the sixth switch transistor

Assignees

• Shanghai Tianma Micro Elect Co

Inventors

• Tseng Chang-Ho
• Leng Chuanli
• Li Yuan

Classifications

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0809

  Several active elements per pixel in active matrix panels · CPC title

• G09G2310/0262

  The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G3/3275

  Details of drivers for data electrodes · CPC title