Differential amplitude detector

Patent metadata

Field	Value
Publication number	US-10241948-B2
Application number	US-201815980559-A
Country	US
Kind code	B2
Filing date	May 15, 2018
Priority date	Jun 30, 2015
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

An example embodiment includes an idle state detection circuit. The idle state detection circuit includes a bias current loop, a rectifying circuit loop, a voltage translating loop, and a filter circuit. The bias current loop provides a rectifying diode a forward current such that the rectifying diode detects an alternating current (AC) signal received from a transmitter via one or more transmission nodes. The rectifying circuit loop stores differential peak to peak amplitude information representative of a peak to peak amplitude of the AC signal in a first capacitor that is electrically coupled to a cathode side of the rectifying diode. The voltage translating loop converts the differential peak to peak amplitude information stored at the first capacitor to a single-end voltage signal across a first resistor that is electrically coupled to the cathode side of the rectifying diode. The filter circuit filters an AC component of the single-end voltage signal.

First claim

What is claimed is:

1. An idle state detection circuit comprising:
a rectifying circuit configured to detect an alternating current (AC) signal from a forward current;
a rectifying circuit loop that includes the rectifying circuit and that is configured to store differential peak to peak amplitude information representative of a peak to peak amplitude of the detected AC signal; and
a voltage translating loop that is configured to convert the differential peak to peak amplitude information to a single-end voltage signal.

2. The idle state detection circuit of claim 1 , further comprising a first capacitive circuit that is electrically coupled to the rectifying circuit, wherein the differential peak to peak amplitude information is stored in the first capacitive circuit.

3. The idle state detection circuit of claim 1 , wherein the AC signal is received from a transmitter via one or more transmission nodes.

4. The idle state detection circuit of claim 3 , further comprising a bias current loop that is configured to provide the rectifying circuit the forward current.

5. The idle state detection circuit of claim 4 , wherein:
the bias current loop includes a first resistor and a second resistor that is electrically coupled between a bias voltage source and to a first transmission node of the one or more transmission nodes; and
the first transmission node is electrically coupled to the rectifying circuit.

6. The idle state detection circuit of claim 1 , further comprising a filter circuit that is configured to filter an AC component of the single-end voltage signal.

7. The idle state detection circuit of claim 6 , wherein:
the filter circuit includes the first resistor and a fourth resistor; and
the fourth resistor is electrically coupled to a second capacitive circuit, the first resistor, and the rectifying circuit.

8. The idle state detection circuit of claim 1 , wherein:
the AC signal includes a radio frequency (RF) signal generated at a peripheral component interconnect express (PCIe) transmitter, and
the single-end voltage signal does not share a common reference node with the RF signal.

9. The idle state detection circuit of claim 1 , wherein the single-end voltage signal is approximately linearly related to the peak to peak amplitude of the AC signal.

10. The idle state detection circuit of claim 9 , wherein:
the voltage translating loop is electrically coupled to a second transmission node and to a reference node.

11. The idle state detection circuit of claim 9 , wherein:
the voltage translating loop is configured to define a bias current and a discharging time constant; and
the bias current and the discharging time constant are defined to reduce an impact of the rectifying circuit loop on the AC signal, to at least partially control a conduction angle of the rectifying circuit, and to vary a magnitude of the bias current though the rectifying circuit.

12. The idle state detection circuit of claim 11 , wherein the discharging time constant is defined according to a time constant expression:
TC= C 1×( R 1+ R 3), in which:

TC represents discharging time constant,
C 1 represents a capacitance of a first capacitor,
R 1 represents a resistance of a first resistor, and
R 3 represents a resistance of a third resistor.

13. The idle state detection circuit of claim 1 , further comprising:
a first transmission node;
a second transmission node;
an intermediate node;
a bias voltage source;
an output node;
a reference node;
a fourth capacitor;
a first capacitor coupled to the second transmission node and to the intermediate node
a fourth capacitor coupled to the second transmission node,
a second resistor coupled to the second transmission node and to the reference node;
a third resistor coupled to the intermediate node and to the reference node;
a fourth resistor coupled to the intermediate node and to the output node;
a second capacitor coupled to the output node and to the reference node; and
a third capacitor coupled to the first transmission node;
wherein:
a first resistor is coupled to the first transmission node and to the bias voltage source;
the rectifying circuit is coupled to the first transmission node and to the intermediate node;
the third capacitor and the fourth capacitor are configured to block DC electrical signals; and
the fourth resistor and the second capacitor are configured to filter an AC component of the DC signal.

14. An amplitude detection portion of a detection circuit that is configured to measure an alternating current (AC) signal, the amplitude detection portion comprising:
a rectifying circuit loop configured to store differential peak to peak amplitude information in a first capacitor, the differential peak to peak amplitude information being representative of a peak to peak amplitude of the AC signal received from a peripheral component interconnect express (PCIe) transmitter;
a first resistor electrically coupled to the rectifying circuit loop, wherein differential peak to peak amplitude information is converted to a single-end voltage signal stored on the first resistor; and
a filter circuit that includes the first resistor, the filter circuit being electrically coupled to the rectifying circuit loop and configured to filter an AC component of the single-end voltage signal.

15. The amplitude detection portion of claim 14 , wherein the single-end voltage signal across the first resistor is approximately linearly related to the peak to peak amplitude of the AC signal.

16. The amplitude detection portion of claim 14 , wherein:
the AC signal includes a radio frequency (RF) signal generated at a peripheral component interconnect express (PCIe) transmitter, and
the single-end voltage signal does not share a common reference node with the RF signal.

17. The amplitude detection portion of claim 14 , wherein:
the rectifying circuit loop includes a rectifying diode and the first capacitor;
the rectifying diode is configured to detect the AC signal from a forward current; and
the first resistor is electrically coupled to an intermediate node between the rectifying diode and the first capacitor.

18. The amplitude detection portion of claim 14 , wherein:
the filter circuit includes the first resistor, a fourth resistor, an output node, and a second capacitor,
the output node is located between the fourth resistor and the second capacitor and is electrically coupled to a controller circuit,
the fourth resistor is electrically coupled to the output node and to the intermediate node, and
the second capacitor is electrically coupled to the output node and a reference node.

19. A peripheral component interconnect express active optical cable (PCIe AOC) comprising:
the amplitude detection portion of claim 18 ; and
a controller circuit coupled to the output node;
wherein:
the controller circuit is configured to receive a DC signal at the output node, compare a magnitude of a voltage of the DC signal to a threshold magnitude of a particular threshold signal, and to generate a control signal configured to transition a PCIe communication link to an electrical idle state based on the comparison.

20. The PCIe AOC of claim 19 , wherein the controller circuit includes a counter circuit configured to count to at least one predetermined time period before generation of the control signal.

Assignees

• Finisar Corp

Inventors

• He Hongdang
• Chen Qin

Classifications

• G06F2213/0026

  PCI express · CPC title

• G06F13/38 Primary

  Information transfer, e.g. on bus (G06F13/14 takes precedence) · CPC title

• G06F13/385 Primary

  for adaptation of a particular data processing system to different peripheral devices · CPC title