Support apparatus and method for processing data and using hardware support for atomic memory transactions

Patent metadata

Field	Value
Publication number	US-10241933-B2
Application number	US-201515123805-A
Country	US
Kind code	B2
Filing date	Mar 4, 2015
Priority date	Mar 6, 2014
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

An asymmetric multiprocessor system includes a plurality of processor cores supporting transactional memory via controllers as well as one or more processor cores which do not support transactional memory via hardware. The controllers respond to receipt of a request for exclusive access to a lock address by determining whether or not their associated processors is currently executing a memory transaction guarded by a lock value stored at that lock address and if their processor is executing such a transaction, then delaying releasing the lock address for exclusive access until a predetermined condition is met. If the processor is not executing such a guarded memory transaction, then the lock address may be unconditionally released for exclusive access. The predetermined condition may be that a threshold delay has been exceeded since the request was received and/or that the request has previously been received and refused a threshold number of times. The request may arise through execution of a transaction start instruction which serves to read a lock address from an architectural register storing the lock address should the processor executing that transaction start instruction not already be executing a pending memory transaction. If the processor is already executing a memory transaction, then the transaction start instruction need not access the lock value stored at the lock address held within the lock address register as it may be assumed that the lock value has already been checked.

First claim

The invention claimed is:

1. Apparatus for processing data and using hardware support for atomic memory transactions, said apparatus comprising:
a plurality of processors, each configured to execute a sequence of program instructions; and
a memory configured to store data values shared by said plurality of processors;
wherein at least one of said plurality of processors is an transactional-memory-supporting processor having a controller configured to monitor access to a lock address within said memory and said controller is configured to respond to a received request from another of said plurality of processors to obtain exclusive access to said lock address by:
(i) when said transactional-memory-supporting processor is executing a memory transaction guarded by said lock address, delaying releasing said lock address for exclusive access until a predetermined condition is met; and
(ii) when said transactional-memory-supporting processor is not executing a memory transaction guarded by said lock address, releasing said lock address for exclusive access independent of said predetermined condition.

2. Apparatus as claimed in claim 1 , wherein said controller is configured to delay releasing said lock address by returning a request refused response to said received request.

3. Apparatus as claimed in claim 1 , wherein said controller is configured to delay releasing said lock address by delaying returning any response to said received request.

4. Apparatus as claimed in claim 1 , wherein said predetermined condition is at least partially that said transactional-memory-supporting processor has received a predetermined number of access requests to said lock address without releasing said lock address.

5. Apparatus as claimed in claim 1 , wherein said predetermined condition is at least partially that said transactional-memory-supporting processor has delayed releasing said lock address for a predetermined time.

6. Apparatus as claimed in claim 1 , wherein said controller is configured to abort said memory transaction guarded by said lock value if said lock address is released before said memory transaction has completed.

7. Apparatus as claimed in claim 1 , wherein said plurality of processors includes at least one transactional-memory-non-supporting processor without said controller.

8. Apparatus as claimed in claim 7 , wherein said transactional-memory-non-supporting processor is configured to execute a sequence of lock acquisition program instructions before commencing execution of a memory transaction guarded by said lock value.

9. Apparatus as claimed in claim 7 , wherein said transactional-memory-non-supporting processor has a lower power consumption and a lower instruction processing performance than said transactional-memory-supporting processor.

10. Apparatus as claimed in claim 1 , wherein said plurality of processors form an asymmetric multiprocessing apparatus.

11. Apparatus as claimed in claim 1 , comprising a plurality of transactional-memory-supporting processors.

12. Apparatus as claimed in claim 11 , wherein said predetermined condition is met if said received request is received from one of said plurality of transactional-memory-supporting processors.

13. Apparatus as claimed in claim 1 , wherein at least one of said plurality of processors comprises:
one or more architectural registers configured to hold parameters specifying configuration of said at least one of said plurality of processors, said one or more architectural registers including a lock address register dedicated to storing said lock address; and
instruction decoder circuitry configured to decode a transaction start instruction indicating starting of a memory transaction and:
(i) if said at least one of said plurality of processors is not executing a memory transaction, then to generate one or more control signals to control reading of said lock address from said lock address register and at least accessing of said lock value stored at said lock address; and
(ii) if said at least one of said plurality of processors is already executing a memory transaction, then proceeding with further processing without accessing of said lock value stored at said lock address.

14. Apparatus as claimed in claim 13 , wherein said apparatus is configured to execute program instructions corresponding to a plurality of different program processes with a given one of said plurality of processors executing a given one of said plurality of program processes for a given period and said lock address register of said given one of said plurality of processors storing a lock address for said given one of said plurality of program processes during said given period.

15. Apparatus for processing data and including hardware support for atomic memory transactions, said apparatus comprising:
a plurality of means for processing, each for executing a sequence of program instructions; and
means for storing data values shared by said plurality of means for processing;
wherein at least one of said plurality of means for processing is an transactional-memory-supporting processor having means for monitoring access to a lock address within said means for storing and for responding to a received request from another of said plurality of means for processing to obtain exclusive access to said lock address by:
(i) when said transactional-memory-supporting processor is executing a memory transaction guarded by said lock address, delaying releasing said lock address for exclusive access until a predetermined condition is met; and
(ii) when said transactional-memory-supporting processor is not executing a memory transaction guarded by said lock address, releasing said lock address for exclusive access independent of said predetermined condition.

16. A method of processing data using hardware support for atomic memory transactions, said method comprising the steps of:
executing a sequence of program instructions using a plurality of processors; and
storing within a memory data values shared by said plurality of processors;
wherein at least one of said plurality of processing means is an transactional-memory-supporting processor that monitors access to a lock address within said memory and responds to a received request from another of said plurality of processors to obtain exclusive access to said lock address by:
(i) when said transactional-memory-supporting processor is executing a memory transaction guarded by said lock address, delaying releasing said lock address for exclusive access until a predetermined condition is met; and
(ii) when said transactional-memory-supporting processor is not executing a memory transaction guarded by said lock address, releasing said lock address for exclusive access independent of said predetermined condition.

17. Apparatus for processing data and providing hardware support for atomic memory transactions, said apparatus comprising:
a plurality of processors, each configured to execute a sequence of program instructions; and
a memory configured to store data values shared by said plurality of processors; wherein
at least a given one of said plurality of processors comprises:
one or more architectural registers configured to hold parameters specifying configuration of said at least one of said plurality of processors, said one or more architectural registers including a lock address register dedicated to storing a lock address serving to control exclusive access to a region of said memory; and
instruction decoder circuitry configured to decode a transaction start instruction indicating startin

Assignees

• Advanced Risc Mach Ltd

Inventors

• Horsnell Matthew James
• Grisenthwaite Richard Roy
• Biles Stuart David

Classifications

• G06F9/526

  Mutual exclusion algorithms · CPC title

• G06F2212/1052

  Security improvement · CPC title

• G06F9/467 Primary

  Transactional memory (G06F9/528 takes precedence) · CPC title

• G06F12/1475 Primary

  in a virtual system, e.g. with translation means · CPC title

• G06F1/329

  by task scheduling · CPC title