Data caching method and computer system

Patent metadata

Field	Value
Publication number	US-10241919-B2
Application number	US-201615347776-A
Country	US
Kind code	B2
Filing date	Nov 9, 2016
Priority date	May 9, 2014
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

A data caching method and a computer system are provided. In the method, when a miss of an access request occurs and a cache needs to determine a to-be-replaced cache line, not only a historical access frequency of the cache line but also a type of a memory corresponding to the cache line needs to be considered. A cache line corresponding to a DRAM type may be preferably replaced, which reduces a caching amount in the cache for data stored in a DRAM and relatively increase a caching amount for data stored in an NVM. For an access request for accessing the data stored in the NVM, corresponding data can be found in the cache whenever possible, thereby reducing cases of reading data from the NVM. Thus, a delay in reading data from the NVM is reduced, and access efficiency is effectively improved.

First claim

What is claimed is:

1. A data caching method performed by a cache processor, comprising:
receiving a data access request for accessing a first data from a processor in a computer system, wherein the computer system comprises a hybrid memory comprising a dynamic random access memory (DRAM) and a nonvolatile memory (NVM);
determining, according to a historical access frequency of a cache line in the cache and a type of a memory corresponding to the cache line, that a plurality of cache lines in the cache meet a first preset condition and the first data is not cached in the cache, wherein the cache lines that meet the first preset condition correspond to the DRAM and each has a historical access frequency that is lower than a preset frequency;
selecting a first cache line from the cache lines that meet the first preset condition;
reading the first data from the hybrid memory according to an access address in the access request; and
replacing the first cache line with a second cache line, the second cache line comprising the first data.

2. The method of claim 1 , wherein:
the determining that a plurality of cache lines in the cache meet the first preset condition comprises determining that the cache lines corresponding to the DRAM are in first M cache lines in a least recently used (LRU) linked list of the cache, each of the first M cache lines being cache lines having a historical access frequency that is lower than the preset frequency, and M being an integer value that is greater than or equal to 2; and
the selecting the first cache line from the cache lines that meet the first preset condition comprises selecting, as the first cache line, a determined cache line corresponding to the DRAM from the first M cache lines when the cache lines corresponding to the DRAM are in the first M cache lines.

3. The method of claim 2 , wherein the determining that the cache lines corresponding to the DRAM are in the first M cache lines comprises determining, according to a location flag bit of each of the first M cache lines in the cache, whether the cache lines corresponding to the DRAM are in the first M cache lines, the location flag bit of the each of the first M cache lines indicating whether a memory corresponding to the each cache line is the DRAM or the NVM.

4. The method of claim 1 , further comprising recording, according to a memory corresponding to the access address, a type of the memory corresponding to the second cache line in a location flag bit of the second cache line.

5. A data caching method performed by a cache processor, comprising:
receiving a data access request for accessing a first data from a processor in a computer system including a hybrid memory, the data access request comprising an access address, and the hybrid memory comprising a dynamic random access memory (DRAM) and a nonvolatile memory (NVM);
determining, according to a historical access frequency of a cache line in the cache and a type of a memory corresponding to the cache line, that a plurality of cache lines that meet a first preset condition are not in the cache and the first data is not cached in the cache, the cache lines that meet the first preset condition corresponding to the DRAM and each having a historical access frequency that is lower than a preset frequency;
determining a plurality of cache lines that meet a second preset condition are in the cache, the cache lines that meet the second preset condition comprising a plurality of unmodified cache lines corresponding to the NVM and each having a historical access frequency that is lower than the preset frequency;
selecting a first cache line from the cache lines that meet the second preset condition;
reading the first data from the hybrid memory according to the access address; and
replacing the first cache line with a second cache line, the second cache line comprising the first data.

6. The method of claim 5 , wherein the determining the cache lines that meet a first preset condition are not in the cache comprises:
determining the cache lines corresponding to the DRAM are not in first M cache lines in a least recently used (LRU) linked list of the cache, each of the first M cache lines being cache lines having a historical access frequency that is lower than the preset frequency, and M being an integer value that is greater than or equal to 2.

7. The method of claim 6 , wherein the determining the cache lines corresponding to the DRAM are not in the first M cache lines comprises determining, according to a location flag bit of each of the first M cache lines in the cache, the cache lines corresponding to the DRAM are not in the first M cache lines, the location flag bit of the each of the first M cache lines indicating whether a memory corresponding to the each cache line is the DRAM or the NVM.

8. The method of claim 7 , wherein the determining the plurality of cache lines that meet the second preset condition are in the cache comprises determining the cache lines that correspond to the NVM and comprise a modify flag bit indicating that the cache lines are unmodified are in first N cache lines in the LRU linked list of the cache, the first N cache lines being cache lines that each have a historical access frequency that is lower than the preset frequency, N being an integer value that is greater than 0 and less than M;
wherein the selecting the first cache line from the cache lines that meet the second preset condition comprises selecting, as the first cache line, a determined cache line corresponding to the NVM and comprising the modify flag bit indicating that the cache line is unmodified from the first N cache lines.

9. The method of claim 5 , further comprising determining that a cache line at the most front end of the LRU linked list is the first cache line when the cache lines that meet the second preset condition are not in the cache.

10. The method of claim 5 , further comprising recording, according to a memory corresponding to the access address, a type of the memory corresponding to the second cache line in a location flag bit of the second cache line.

11. A computer system, comprising:
a processor,
a hybrid memory comprising a dynamic random access memory (DRAM) and a nonvolatile memory (NVM);
a cache comprising a cache processor coupled to the processor in the computer system and the hybrid memory, the cache processor configured to:
receive a data access request for accessing a first data from the processor, the data access request comprising an access address;
determine, according to a historical access frequency of a cache line in the cache and a type of a memory corresponding to the cache line, whether cache lines in the cache meet a first preset condition when the first data is not cached in the cache, the cache lines that meet the first preset condition corresponding to the DRAM and each having a historical access frequency that is lower than a preset frequency and;
select a first cache line from the cache lines that meet the first preset condition when the cache lines that meet the first preset condition are in the cache;
read the first data from the hybrid memory according to the access address; and
replace the first cache line with a second cache line, the second cache line comprising the first data.

12. The computer system of claim 11 , wherein the cache processor is configured to:
determine whether the cache lines corresponding to the DRAM are in first M cache lines in a least recently used (LRU) linked list of the cache, each of the first M cache lines being cache lines having a historical access frequency that is lower than the preset frequency, and M being an integer value that is greater than

Assignees

• Huawei Tech Co Ltd

Inventors

• Wei Wei
• Zhang Lixin
• Xiong Jin
• Jiang Dejun

Classifications

• G06F3/065

  Replication mechanisms · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F12/122

  of the least frequently used [LFU] type, e.g. with individual count value · CPC title

• G06F3/0631

  by allocating resources to storage systems · CPC title