Memory subsystem to augment physical memory of a computing system

Patent metadata

Field	Value
Publication number	US-10241906-B1
Application number	US-201615224534-A
Country	US
Kind code	B1
Filing date	Jul 30, 2016
Priority date	Jul 30, 2016
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

Systems and methods are provided for implementing a memory subsystem to augment physical memory of a computing system. For example, a system comprises a memory subsystem, and a computing system coupled to the memory subsystem. The computing system comprises a processor, a first memory module, and a second memory module. The first memory module comprises random access memory which is utilized by the processor to store data associated with an application executing on the computing system. The second memory module comprises control logic circuitry that is configured to control access to the memory subsystem on behalf of the processor to store and retrieve data associated with the application executing on the computing system.

First claim

What is claimed is:

1. A system comprising:
a memory appliance which comprises an array of memory devices and control logic circuitry configured to control access to the array of memory devices; and
a server node coupled to the memory appliance, wherein the memory appliance is separate from the server node and is configured as a memory subsystem for the server node to augment a system memory of the server node, wherein the server node comprises:
a processor comprising a memory controller;
a first memory module comprising the system memory of the server node, which is utilized by the memory controller of the processor to store data associated with an application executing on the server node; and
a second memory module comprising control logic circuitry that is configured to control access to the memory appliance on behalf of the memory controller of the processor to store data associated with the application executing on the server node;
wherein the memory controller of the processor communicates with the first memory module and the second memory module using a same first memory interface;
wherein the second memory module communicates with the control logic circuitry of the memory appliance using a second memory interface, which is different from the first memory interface; and
wherein the second memory module is configured to (i) receive a data access request from the memory controller of the processor to access data in the array of memory devices of the memory appliance and (ii) utilize the second memory interface to communicate with the control logic circuitry of the memory appliance and execute the data access request to access data in the array of memory devices of the memory appliance on behalf of the memory controller of the processor.

2. The system of claim 1 , wherein the second memory interface comprises a high-speed serial interface.

3. The system of claim 1 , wherein the first memory module and the second memory module comprise dual in-line memory modules.

4. The system of claim 1 , wherein the second memory module comprises a control register to store configuration data that is used by the control logic circuitry to access the memory appliance.

5. The system of claim 4 , wherein the configuration data is stored in the control register of the second memory module under control of an operating system of the server node to enable exception handling by the processor.

6. The system of claim 1 , wherein the second memory module comprises a control register to store address translation data that is used by the control logic circuitry of the second memory module to translate between a physical address and a local physical address associated with the array of memory devices of the memory appliance.

7. The system of claim 1 , wherein the second memory module further comprises random access memory which is utilized by the processor to store data associated with the application executing on the server node.

8. The system of claim 1 , wherein the array of memory devices of the memory appliance comprises random access memory devices.

9. The system of claim 1 , wherein the array of memory devices of the memory appliance comprises flash memory devices.

10. The system of claim 1 , wherein the control logic circuitry of the memory appliance is configured to control access to the array of memory devices of the memory appliance based on data access commands received from the second memory module on the server node.

11. The system of claim 1 , wherein the memory appliance is configured as a virtual memory backing store for a virtual memory system of an operating system of the server node.

12. The system of claim 1 , wherein the memory appliance is configured as a block storage device, wherein a data block that is cached in the first memory module is stored in a corresponding memory location of the array of memory devices of the memory appliance at the same time using a write-through operation.

13. The system of claim 1 , further comprising an out-of-band management network configured to enable communication between the server node and the memory appliance.

14. The system of claim 1 , wherein the memory appliance comprises a rack-mounted memory unit that is mounted in an equipment rack, wherein the server node comprises a rack-mounted server node that is mounted in the equipment rack, and wherein the rack-mounted memory unit and the rack-mounted server node are coupled together using at least one of metallic wiring and optical fiber wiring.

15. A method, comprising:
utilizing, by a memory controller of a processor of a server node, a first memory module comprising a system memory of the server node to store data associated with an application executing on the server node; and
utilizing, by the memory controller of the processor, a second memory module which comprises control logic circuitry configured to access a memory appliance coupled to the server node, on behalf of the processor, to store data associated with the application executing on the server node;
wherein the memory appliance comprises an array of memory devices and control logic circuitry configured to control access to the array of memory devices;
wherein memory appliance is coupled to and separate from the server node, and configured as a memory subsystem for the server node to augment the system memory of the server node;
wherein the first memory module and the second memory module reside on the server node;
wherein the memory controller of the processor communicates with the first memory module and the second memory module using a same first memory interface;
wherein the second memory module communicates with the control logic circuitry of the memory appliance using a second memory interface, which is different from the first memory interface; and
wherein the second memory module is configured to (i) receive a data access request from the memory controller of the processor to access data in the array of memory devices of the memory appliance and (ii) utilize the second memory interface to communicate with the control logic circuitry of the memory appliance and execute the data access request to access data in the array of memory devices of the memory appliance on behalf of the memory controller of the processor.

16. The method of claim 15 , further comprising storing, by the processor, configuration data in a control register of the second memory module, which is utilized by the control logic circuitry of the second memory module to access the memory appliance.

17. The method of claim 15 , further comprising:
storing address translation data in a control register of the second memory module, which is utilized by the control logic circuitry of the second memory module to translate between a physical address and a local physical address associated with the array of memory devices of the memory appliance; and
storing data associated with the application executing on the server node in a random access memory of the second memory module.

18. The method of claim 15 , comprising configuring the memory appliance as a virtual memory backing store for a virtual memory system of an operating system of the server node.

19. The method of claim 15 , comprising configuring the memory appliance as a block storage device, wherein a data block that is cached in the first memory module is stored in a corresponding memory location in the array of memory devices of the memory appliance at the same time using a write-through operation.

20. An article of manufacture compr

Assignees

• Emc Corp
• Emc Ip Holding Co Llc

Inventors

• Robillard Michael
• Savic Dragan
• Michaud Adrian
• Beauchamp Robert

Classifications

• G06F2212/154

  Networked environment · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/0873 Primary

  Mapping of cache memory to specific storage devices or parts thereof · CPC title

• G06F2212/651

  Multi-level translation tables · CPC title

• G06F2212/1024

  Latency reduction · CPC title