Control transfer override

Patent metadata

Field	Value
Publication number	US-10241787-B2
Application number	US-201414231509-A
Country	US
Kind code	B2
Filing date	Mar 31, 2014
Priority date	Mar 31, 2014
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

Embodiments of an invention for control transfer overrides are disclosed. In one embodiment, a processor includes an instruction unit to receive a control transfer instruction. The instruction unit includes a transfer override register to provide an alternative target for the control transfer instruction.

First claim

What is claimed is:

1. A method comprising:
programming, by software, a transfer override register in a processor to specify an alternative target address of a control transfer instruction having an original target address;
enabling the transfer override register;
issuing, to the processor, the control transfer instruction;
loading, by an instruction fetch circuit in the processor in response to the control transfer instruction, an instruction register in the processor from the alternative target address instead of the original target address;
calculating, in response to receiving the control transfer instruction when the programmable transfer override register is enabled, the original target address of the control transfer instruction; and
storing, in response to receiving the control transfer instruction when the programmable transfer override register is enabled, the original target address of the control transfer instruction in an alternative instruction pointer register.

2. The method of claim 1 , further comprising programming a configuration register to enable the transfer override register.

3. The method of claim 2 , wherein control is transferred to the original target address instead of to the alternative target address is the transfer override register is disabled.

4. The method of claim 2 , further comprising storing a control transfer instruction destination.

5. The method of claim 4 , wherein storing a control transfer instruction destination includes storing a pointer to the original target address.

6. The method of claim 1 , wherein the alternative target address of the control transfer instruction is a location within the security layer.

7. The method of claim 6 , further comprising examining, by the security layer, code associated with the original target address.

8. The method of claim 7 , further comprising determining, by the security layer, whether to transfer control to the original target address, and transferring, in response to the determining, control to the original target address.

9. A processor comprising:
an instruction unit to receive a control transfer instruction, the instruction unit including an instruction pointer register;
an alternative instruction pointer register;
an instruction register in which to store a current instruction to be executed by the processor;
a programmable transfer override register to specify an alternative target address of a control transfer instruction;
an instruction fetch circuit to load, in response to receiving the control transfer instruction, the instruction register from the alternative target address if the programmable transfer override register is enabled and from an original target address of the control transfer instruction if the programmable transfer override register is disabled; and
hardware to, in response to receiving the control transfer instruction when the programmable transfer override register is enabled, calculate the original target address of the control transfer instruction and store the original target address of the control transfer instruction in the alternative instruction pointer register.

10. The processor of claim 1 , further comprising transfer override control logic to store a control transfer instruction destination.

11. The processor of claim 10 , wherein storing the control transfer instruction destination includes storing a pointer to the original target address.

12. The processor of claim 1 , further comprising a configuration register to be programmed to enable the programmable transfer override register.

13. The processor of claim 12 , wherein the configuration register includes one or more fields to provide information to selectively enable the programmable transfer override register.

14. A system comprising:
a memory in which to store first software and second software, wherein the first software includes a control transfer instruction having an original target address in the second software; and
a processor including
an instruction unit to receive a control transfer instruction, the instruction unit including
an instruction pointer register;
an alternative instruction pointer register;
an instruction register in which to store a current instruction to be executed by the processor;
a programmable transfer override register to specify an alternative target address of the control transfer instruction;
an instruction fetch circuit to load, in response to receiving the control transfer instruction, the instruction register from the alternative target address if the programmable transfer override register is enabled and from the original target address of the control transfer instruction if the programmable transfer override register is disabled; and
hardware to, in response to receiving the control transfer instruction when the programmable transfer override register is enabled, calculate the original target address of the control transfer instruction and store the original target address of the control transfer instruction in the alternative instruction pointer register.

15. The system of claim 14 , wherein the memory is also in which to store the security layer, and the alternative target address is within the security layer.

Assignees

• Intel Corp

Inventors

• Caprioli Paul

Classifications

• G06F21/72

  in cryptographic circuits · CPC title

• G06F9/00 Primary

  Arrangements for program control, e.g. control units (program control for peripheral devices G06F13/10) · CPC title

• G06F21/00

  Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity · CPC title

• G06F21/52 Primary

  during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} · CPC title

• G06F11/00

  Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00) · CPC title